ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 151
ALXD800EEXJCVD C3
Manufacturer Part Number
ALXD800EEXJCVD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJCVD_C3.pdf
(680 pages)
Specifications of ALXD800EEXJCVD C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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CPU Core Register Descriptions
AMD Geode™ LX Processors Data Book
Bits
8
7
6
5
4
3
2
1
0
Name
ICD
TUS
RSVD
L0D
L0IN
RSVD
SER
FLD
TBE
Description
Instruction Cache Disable. Completely disable L0 and L1 instruction caches. Contents
of cache is not modified and no cache entry is read.
0: Use standard x86 cacheability rules. (Default)
1: Instruction cache will always generate a miss.
Translation Look-aside Buffer Updates Select. Select L1 TLB updates (not L1 TLB
evictions) to go out on the IM’s Translation Bus. Otherwise, only L1 TLB evictions go out
on IM’s Translation Bus. IM only supports either updates or evictions going out on the
bus, but not both.
0: Disable. (Default)
1: Enable.
Reserved. Always write zero.
L0 Cache Disable.
0: Disable. (Default)
1: Enable.
L0 Cache Invalidate.
0: Disable. (Default)
1: Enable.
Reserved.
Serialize Cache State Machine. If this bit is set, only one outstanding request to the bus
controller is allowed at one time.
0: Disable. (Default)
1: Enable.
Flushing Disable. Disable full flushing of the IM (including outstanding bus controller
requests) on IF aborts. If this bit is disabled, the IM only aborts requests that have not
already gone out to the bus controller.
0: Enable. (Default)
1: Disable.
Treatment Bus Enable. If this bit is set, then the treatment bus from the GLCP is able to
modify the IM’s behavior.
0: Disable. (Default)
1: Enable
IM_CONFIG_MSR Bit Descriptions (Continued)
33234H
151
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