ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 502

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.10.2.18 VIP Task B VBI Odd Base/VBI Start (VIP_TASK_B_VBI_ODD_BASE_VBI_START)
VIP Memory Offset 44h
Type
Reset Value
6.10.2.19 VIP Task B Data Pitch/Vertical Start Even (VIP_TASK_B_DATA_PITCH_VERT_START_EVEN)
VIP Memory Offset 48h
Type
Reset Value
502
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:28
11:0
31:0
11:0
Bit
Bit
Bit
RSVD
Name
VBI_END
Name
TASK_B_VBI_
DATA_ODD_
BASE
VBI_START
Name
RSVD
VIP_TASK_B_VBI_EVEN_BASE_VBI_END Bit Descriptions (Continued)
R/W
00000000h
R/W
00000000h
VIP_TASK_B_DATA_PITCH_VERT_START_EVEN BIT Descriptions
33234H
VIP_TASK_B_DATA_PITCH_VERT_START_EVEN Register Map
VIP_TASK_B_VBI_ODD_BASE_VBI_START BIt Descriptions
VIP_TASK_B_VBI_ODD_BASE_VBI_START Register Map
VERTICAL_END_EVEN
TASK_B_VBI_DATA_ODD_BASE_VBI_START (for 601 type modes)
Description
VBI End. This register is redefined in BT.601 mode. In BT.601 type input modes, timing
is derived from the external HSYNC and VSYNC inputs. This value specifies what line
the VBI data ends in each field/frame. The end of VBI data is reached when the number
of lines from the falling edge of VSYNC equals this value. See Figure 6-48 "BT.601 Mode
Vertical Timing" on page 473 for additional detail.
Description
Reserved.
Description
Task B VBI Odd Base Address. This register specifies the base address in graphics
memory where VBI data for odd fields is stored. Changes to this register take effect at
the beginning of the next field. This value must be 32-byte aligned. (Bits [4:0] are
required to be 00000.)
Note:
VBI Start. This register is redefined in BT.601 mode. In BT.601 type input modes, timing
is derived from the external HSYNC and VSYNC inputs. This value specifies what line
the VBI data starts in each field/frame. The start of VBI data begins when the number of
lines from the leading edge of VSYNC equals this value. See Figure 6-48 "BT.601 Mode
Vertical Timing" on page 473 for additional detail.
This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not
Updated bit (VIP Memory Offset 08h[16]) is set to 1. The VBI Odd Base Address
register is not updated at this point. When the first data of the next field is cap-
tured, the pending values of all base registers are written to the appropriate base
registers, and the VBI Base Register Not Updated bit is cleared.
TASK_B_DATA_PITCH_VERT_START_EVEN
AMD Geode™ LX Processors Data Book
Video Input Port Register Descriptions
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0