ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 425

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Processor Register Descriptions
6.8.3.4
VP Memory Offset 018h
Type
Reset Value
Note 1. V_TOTAL and V_SYNC_END are the values written in the Display Controller module registers.
6.8.3.5
VP Memory Offset 020h
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:27
26:16
15:11
63:32
10:0
Bit
Bit
31
RSVD
Video Y Position (VY)
Video Scale (SCL)
Name
RSVD (RO)
VID_Y_END
RSVD (RO)
VID_Y_START
RSVD (RO)
GP (RO)
Name
R/W
00000000_00000000h
R/W
00000000_00000000h
RSVD
Description
Reserved (Read Only). Reads back as 0.
Video Y End Position. Represents the vertical end position of the video window. This
value is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 2. (Note 1)
Reserved (Read Only). Reads back as 0.
Video Y Start Position. Represents the vertical start position of the video window. This
register is programmed relative to CRT Vertical sync input (not the physical screen posi-
tion). This value is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1. (Note 1)
Description
Reserved (Read Only). Reads back as 0.
GLIU Passed (Read Only). This bit set indicates the GLIU line buffer fill has been
passed by the Dot display. Screen display tearing might occur. This bit clears on read.
This bit is typically set if during vertical downscale, the 2nd line buffer fill hasn’t started
before the Dot display has started. This indicates an error in that the GLIU line buffer fill
can’t keep up with the Dot clock display rate.
VID_Y_END
SCL Bit Descriptions
VY Bit Descriptions
SCL Register Map
VY Register Map
RSVD
RSVD
RSVD
9
9
8
8
33234H
7
7
VID_Y_START
6
6
VSL
5
5
4
4
3
3
2
2
1
1
425
0
0