ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 356

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.17
6.6.17.1 VGA Miscellaneous Output
Read Address
Write Address
Type
Reset Value
356
Bit
Bit
3:2
2
1
0
7
6
5
4
1
0
VGA Block Standard Registers
Name
VBLANK_SMI
ISR0_SMI
MISC_SMI
Name
VSYNC_POL
HSYNC_POL
PAGE
RSVD
CLK_SEL
RAM_EN
ID_ADDR_SEL
3CCh
3C2h
R/W
02h
33234H
VGA Miscellaneous Output Register Bit Descriptions
Description
VBLANK SMI. If = 1, an SMI was generated due to leading edge vertical blank.
Input Status Register 0 SMI. If = 1, an SMI was generated from an I/O IN to Input Status
Register 0.
Miscellaneous Output Register SMI. If = 1, an SMI was generated from an I/O OUT to
the Miscellaneous Output Register.
Description
Vertical Sync Polarity. Selects a positive-going VSYNC pulse (bit = 0) or a negative-
going VSYNC pulse (bit = 1).
Horizontal Sync Polarity. Selects a positive-going HSYNC pulse (bit = 0) or a negative-
going HSYNC pulse (bit = 1).
Page Bit. This bit is used to replace memory address bit A0 as the LSB when bit 1 of the
Miscellaneous register (Index 06h[1]) in the VGA Graphics Controller is set to 1.
Reserved.
Clock Select. Selects the VGA pixel clock source. Writes to this register will directly
affect the frequency generated by the Dot clock PLLs. The value of this register is sam-
pled when it is written; The Dot clock frequency can be overridden by subsequent writes
to the Dot clock PLL controls. If the VGA is disabled or in fixed timing mode, the Dot clock
frequency is NOT affected by writes to this register.
00: Selects clock for 640/320 pixels per line (25.175 MHz Dot clock).
01: Selects clock for 720/360 pixels per line (28.325 MHz Dot clock).
10: Reserved.
11: Reserved.
RAM Enable. Enables the video frame buffer address decode when set to 1.
I/O Address Select. Determines the I/O address of the CRTC Index and Data registers
(Index 3?4h and 3?5h), Feature Control register (Index 3?Ah), and Input Status Register
1 (Index 3?Ah) as follows: ? = B when bit set to 0 (MDA I/O address emulation), ? = D
when bit set to 1 (CGA address emulation).
VGA_STATUS Bit Descriptions (Continued)
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book