ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 149

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.49 Extended Flags MSR (EFLAG_MSR)
MSR Address
Type
Reset Value
5.5.2.50 Control Register 0 MSR (CR0_MSR)
MSR Address
Type
Reset Value
This is the standard x86 Control Register 0 (CR0). CR1, CR2, CR3, and CR4 are located at MSRs 00001881h-00001884h
(see Section 5.5.2.74 on page 172). The contents of CR0-CR4 should only be accessed using the MOV instruction. They
are mentioned here for completeness only. See Section 5.4.1 “Control Registers” on page 95 for bit descriptions.
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:22
20:19
13:12
Bit
21
18
17
16
15
14
11
10
9
8
7
6
5
4
3
2
1
0
Name
RSVD
ID
RSVD
AC
VM
RF
RSVD
NT
IOPL
OF
DF
IF
TF
SF
ZF
RSVD
AF
RSVD
PF
RSVD
CF
RSVD (0)
00001418h
R/W
00000000_00000002h
00001420h
R/W
00000000_60000010h
Description
Reserved. (Default = 0)
Identification Flag. (Default = 0)
Reserved. (Default = 0)
Alignment Check Flag. (Default = 0)
Virtual 8086 Flag. (Default = 0)
Resume Flag. Disable instruction address breakpoints. (Default = 0)
Reserved. (Default = 0)
Nested Task Flag. (Default = 0)
Input/Output Privilege Level. (Default = 0)
Overflow Flag. (Default = 0)
Repeated-String Direction Flag. (Default = 0)
Eternal Maskable Interrupt Enable. (Default = 0)
Single-Step Trap Flag. (Default = 0)
Sign Flag. (Default = 0)
Zero Flag. (Default = 0)
Reserved. (Default = 0)
Auxiliary Carry Flag. (Default = 0)
Reserved. (Default = 0)
Parity Flag. (Default = 0)
Reserved. (Default = 1)
Carry Flag. (Default = 1)
ID RSVD
EFLAG_MSR Bit Descriptions
(0)
EFLAG_MSR Register Map
AC VM RF
RSVD
NT
IOPL OF DF IF TF SF ZF
9
8
33234H
7
6
5
AF
4
3
PF
2
1
149
CF
0