ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 210

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.1
The GeodeLink™ Memory Controller (GLMC) module sup-
ports the Unified Memory Architecture (UMA) of the
AMD Geode™ LX processor and controls a 64-bit DDR
SDRAM interface without any external buffering. The inter-
nal block diagram of the GLMC is shown in Figure 6-2.
The SDRAM memory array contains both the main system
memory and the graphics frame buffer. Up to four module
banks of SDRAM are supported. Each module bank can
have two or four component banks depending on the mem-
ory size and organization. The maximum configuration is
210
Data Path
Response
Request
Packet
Packet
Packet
GLUI0
GLUI0
GLUI0
GeodeLink™ Memory Controller
Write
Adrs/Ctl
33234H
Gen
Write
Write
Write
Buf
Buf
Buf
Figure 6-2. GLMC Block Diagram
Bank/
Logic
Page
Req
Buf
Refresh
Req
Buf
Arbiter
four module banks with four component banks, each pro-
viding a total of 16 open banks with the maximum memory
size supported being 2 GB.
The GLMC handles multiple requests for memory data
from the CPU Core, the Graphics Processor, the Display
Controller, and the external PCI bus via the GeodeLink
Interface Units (GLIUs). The GLMC contains extensive
buffering logic that helps minimize contention for memory
bandwidth between the various requests.
Write
Response
MemRd
Response
MSR
Rd Resp
Capture/
Registers
Resync
MSR
AMD Geode™ LX Processors Data Book
SDRAM IF
GeodeLink™ Memory Controller
R_DATA
Control
W_DATA
Data
DQ
DQM
DQS
RAS
CAS
WE
CKE
MA
BA
CS