ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 344

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.10.4 DC Filter Coefficient Data Register 2 (DC_FILT_COEFF2)
DC Memory Offset 09Ch
Type
Reset Value
Any read or write of this register causes a read or write of the horizontal or filter coefficient RAM. If this occurs while the dis-
play is active, improper filtering of an output pixel can occur, which may cause temporary visual artifacts (speckling). To
avoid this, either disable the display or avoid accessing this register unless during vertical blank.
6.6.11
6.6.11.1 DC VBI Even Control (DC_VBI_EVEN_CTL)
DC Memory Offset 0A0h
Type
Reset Value
Settings written to this register do not take effect until the start of the following frame or interlaced field.
344
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:20
19:10
Bit
9:0
Bit
31
30
29
VBI Control Registers
Name
RSVD
TAP5
TAP4
Name
VBI_SIG_EN
VBI_16
VBI_UP
R/W
xxxxxxxxh
R/W
xxxxxxxxh
RSVD
33234H
Description
Reserved. Set to 0. This field is used only when reading or writing the Line Buffer Regis-
ter.
Tap 5 Coefficient. This coefficient is used for the fifth tap (rightmost) in the horizontal fil-
ter.
Tap 4 Coefficient. This coefficient is used for the fourth tap (second from the right) in the
horizontal filter.
Description
VBI Signature Enable. This bit allows the CRC engine at the output of the DC to be
used to check VBI data instead of graphics data. When this bit is set, the CRC is gener-
ated based only on VBI data; when cleared, only graphics data is used for the CRC cal-
culation.
VBI 16-bit Enable. When set, VBI data is sent 16 bits per Dot clock. When clear, VBI
data is sent 8 bits per Dot clock.
VBI Upscale. When set, the VBI data is upscaled by 2. This is accomplished by repeat-
ing data twice.
DC_VBI_EVEN_CTL Bit Descriptions
DC_FILT_COEFF2 Bit Descriptions
DC_VBI_EVEN_CTL Register Map
DC_FILT_COEFF2 Register Map
VBI_EVEN_OFFSET
TAP5
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
9
9
8
8
7
7
6
6
5
5
TAP4
4
4
3
3
2
2
1
1
0
0
0