ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 100

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

100
0000132Ch
00001110h
00001140h
00001210h
00001211h
00001212h
00001213h
00001250h
00001301h
00001302h
00001310h
00001311h
00001312h
00001313h
00001320h
00001321h
00001322h
00001323h
00001324h
00001325h
00001326h
00001327h
00001328h
00001329h
0000132Ah
0000132Bh
00001330h
00001331h
00001332h
00001333h
00001334h
Address
MSR
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
33234H
Table 5-13. CPU Core Specific MSRs Summary (Continued)
Register Name
IF Sequential Count MRS (IF_SEQCOUNT_MSR)
IF Built-In Self-Test MSR (IF_BIST_MSR)
Exception Unit (XC) Configuration MSR
(XC_CONFIG_MSR)
XC Mode MSR (XC_MODE_MSR)
XC History MSR (XC_HIST_MSR)
XC Microcode Address MSR (XC_UADDR_MSR)
ID Configuration MSR (ID_CONFIG_MSR)
SMM Control MSR (SMM_CTL_MSR)
Debug Management Interrupt (DMI) Control Reg-
ister
Temporary 0 MSR (TEMP0_MSR)
Temporary 1 MSR (TEMP1_MSR)
Temporary 2 MSR (TEMP2_MSR)
Temporary 3 MSR (TEMP3_MSR)
ES Segment Selector/Flags Register
(ES_SEL_MSR)
CS Segment Selector/Flags Register
(CS_SEL_MSR)
SS Segment Selector/Flags Register
(SS_SEL_MSR)
DS Segment Selector/Flags Register
(DS_SEL_MSR)
FS Segment Selector/Flags Register
(FS_SEL_MSR)
GS Segment Selector/Flags Register
(GS_SEL_MSR)
LDT Segment Selector/Flags Register
(LDT_SEL_MSR)
Temp Segment Selector/Flags Register
(TM_SEL_MSR)
TSS Segment Selector/Flags Register
(TSS_SEL_MSR)
IDT Segment Selector/Flags Register
(IDT_SEL_MSR)
GDT Segment Selector/Flags Register
(GDT_SEL_MSR)
SMM Header MSR (SMM_HDR_MSR)
DMM Header MSR (DMM_HDR_MSR)
ES Segment Base/Limit MSR (ES_BASE_MSR)
CS Segment Base/Limit MSR (CS_BASE_MSR)
SS Segment Base/Limit MSR (SS_BASE_MSR)
DS Segment Base/Limit MSR (DS_BASE_MSR)
FS Segment Base/Limit MSR (FS_BASE_MSR)
AMD Geode™ LX Processors Data Book
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000002h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
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Reset Value
CPU Core Register Descriptions
Reference
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