ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 552

no-image

ALXD800EEXJCVD C3

Manufacturer Part Number
ALXD800EEXJCVD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of ALXD800EEXJCVD C3

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
6.14.2.10 GLCP Clock Active (GLCP_CLKACTIVE)
MSR Address
Type
Reset Value
See "GLCP_CLKOFF Bit Descriptions" on page 551 for bit descriptions.
552
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
11
10
9
8
7
6
5
4
3
2
1
0
Name
DCDOT_0
GLIU0_1
GLIU0_0
GP
GLMC
DRAM
BC_GLIU
BC_VA
MSS
IPIPE
FPUFAST
FPUSLOW
4C000011h
RO
Input Determined
33234H
GLCP_CLKOFF Bit Descriptions (Continued)
Description
DC Dot Clock Off. When set, disables DC Dot Clock 0 (DC).
GLIU0Clock Off. When set, disables main clock to primary GLIU.
GLIU0 Timer Logic Clock Off. When set, disables clock to timer logic of primary
GLIU.
GP Clock Off. When set, disables GP clock (GLIU).
GLMC Clock Off. When set, disables GLIU clock to memory controller.
DRAM Clocks Off. When set, disables external DRAM clocks (and, hence, feedback
clocks).
Bus Controller Clock Off. When set, disables clock to CPU bus controller block.
CPU to Bus Controller Clock Off. When set, disables CPU clock to bus controller
block.
CPU to MSS Clock Off. When set, disables CPU clock to MSS block.
CPU to IPIPE Clock Off. When set, disable CPU clock to IPIPE block.
FPU Fast Clock Off. When set, disables the fast FPU clock.
FPU Clock Off. When set, disables the slow CPU clock to FPU.
GLCP_CLKACTIVE Register Map
RSVD
GeodeLink™ Control Processor Register Descriptions
AMD Geode™ LX Processors Data Book
9
8
7
6
5
4
3
2
1
0

Related parts for ALXD800EEXJCVD C3