ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 254

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.4
The registers associated with the Graphics Processor (GP)
are the Standard GeodeLink™ Device (GLD) MSRs and
Graphics Processor Configuration registers. Table 6-28
and Table 6-29 are register summary tables that include
reset values and page references where the bit descrip-
tions are provided.
The Standard GLD MSRs (accessed via the RDMSR and
WRMSR instructions) control the Graphics Processor’s
behavior as a GLIU module. These registers should be
programmed at configuration time and left alone thereafter.
They do not need to be modified by software to set up any
of the graphics primitives. The MSRs are 64 bits wide,
although not all bits are used in each register. Unused bits
marked as “write as read” return the value that was last
written to them. All other unused bits return 0.
All of the GP registers are accessible by the CPU through
memory mapped reads and writes on the GLIU. Note that
due to the pipelining operation of the GP, the value
returned during a read is the value stored in the slave reg-
ister, while the value in the master register is the actual
value being used by an ongoing BLT or vector operation.
254
MSR Address
GP Memory
A0002000h
A0002001h
A0002002h
A0002003h
A0002004h
A0002005h
Offset
0Ch
0Ch
00h
04h
04h
08h
Graphics Processor Register Definitions
Type
R/W
R/W
R/W
R/W
R/W
Table 6-29. Graphics Processor Configuration Register Summary
R/W
Type
33234H
R/W
R/W
R/W
R/W
R/W
RO
Table 6-28. Standard GeodeLink™ Device MSRs Summary
Group
Address Config
Address Config
Vector Config
Address Config
BLT Config
Vector Config
Register Name
GLD Capabilities MSR
(GLD_MSR_CAP)
GLD Master Configuration MSR
(GLD_MSR_CONFIG)
GLD SMI MSR (GLD_MSR_SMI)
GLD Error MSR
(GLD_MSR_ERROR)
GLD Power Management MSR
(GLD_MSR_PM)
GLD Diagnostic MSR
(GLD_MSR_DIAG)
Register Name
Destination Offset
(GP_DST_OFFSET)
Source Offset
(GP_SRC_OFFSET)
Vector Error (GP_VEC_ERR)
Stride (GP_STRIDE)
BLT Width/Height
(GP_WID_HEIGHT)
Vector Length (GP_VEC_LEN)
Also note that the command buffer has the ability to write
into the slave registers. There is no reason, therefore, to
read
GP_INT_CNTRL, and command buffer registers while the
command buffer is active.
Reserved bits, marked as “write as read,” indicate that
there is a real register backing those bits, which may be
used in some future implementation of the GP. Reserved
register bits that do not have a register backing them
always return a 0, regardless of what value software
decides to write into them.
The GP register space occupies 4 KB of the memory map.
The bottom 256 bytes are defined as access to GP’s pri-
mary registers. The remainder of the lower 1K of address
space is used to alias the host source register for the
source channel, allowing REP MOVS access. The upper
3K of address space is used to alias the host source regis-
ter for channel 3. This is the only aliasing that is supported
by the GP, so all register accesses should use the full 12-
bit offset.
registers
00000000_0003D4xxh
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
other
Reset Value
Graphics Processor Register Definitions
AMD Geode™ LX Processors Data Book
than
Reset Value
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
the
GP_BLT_STATUS,
Reference
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Reference
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