IP-CPRI Altera, IP-CPRI Datasheet - Page 87

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Signals
CPRI MAP Interface Signals
Table 5–9. CPRI MII Transmitter Interface Signals (Part 2 of 2)
CPRI MAP Interface Signals
Table 5–10. CPRI MAP Receiver Interface Signals (Part 1 of 2)
December 2010 Altera Corporation
cpri_mii_txd[3:0]
cpri_mii_txrd
map{23…0}_rx_clk
map{23…0}_rx_reset
map{23…0}_rx_ready
map{23…0}_rx_data[31:0]
CPRI MAP Receiver Signals
Signal
f
Signal
Table 5–10
the CPRI MegaCore function. The CPRI MAP interfaces are implemented as
Avalon-ST interfaces.
Refer to the
Table 5–10
Input
Output
Direction
and
lists the CPRI MAP receiver interface signals.
Avalon Interface Specifications
Ethernet transmit nibble data. The data transmitted from the external Ethernet
block to the CPRI MegaCore function, for transmission on the CPRI link. This input
bus is synchronous to the rising edge of the cpri_clkout clock.
Ethernet read request. Indicates that the MII interface block is ready to read data on
cpri_mii_txd[3:0]. Valid data is recognized 2 cpri_mii_txclk cycles after
cpri_mii_txen is asserted in response to cpri_mii_txrd. The cpri_mii_txrd
signal remains asserted for 2 cpri_mii_txclk cycles following deassertion of
cpri_mii_txen. Deasserting cpri_mii_txrd while cpri_mii_txen is still
asserted backpressures the external Ethernet block.
Table 5–11
Direction
Input
Input
Input
Output
list the signals used by the CPRI MAP interface modules of
Clock signal for each antenna-carrier interface.
Reset signal for each antenna-carrier interface. This reset is
associated with the mapN_rx_clk clock.
mapN_rx_reset can be asserted asynchronously, but must stay
asserted at least one mapN_rx_clk cycle and must be
deasserted synchronously with mapN_rx_clk. Refer to
Figure 4–8 on page 4–14
synchronous deassertion of a reset signal.
Read-ready signal for each antenna-carrier interface. Indicates to
the MegaCore function that the data channel is ready to receive
data on the next clock cycle. Asserted by the sink to mark ready
cycles, which are cycles in which transfers can occur. If ready is
asserted on cycle N, the cycle (N+READY_LATENCY) is a ready
cycle. The CPRI MAP receiver interface is designed for
READY_LATENCY equal to 0. In synchronous buffer mode, this
signal must be held high continuously.
32-bit read data being transmitted on each antenna-carrier
interface. Data is valid one mapN_rx_clk clock cycle after the
read-ready bit is asserted. Bits [15:0] are the I component of the
IQ sample. Bits [31:16] are the Q component of the IQ sample.
for details about the Avalon-ST interface.
Description
for a circuit that shows how to enforce
Description
CPRI MegaCore Function User Guide
5–7