IP-CPRI Altera, IP-CPRI Datasheet - Page 70

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–46
Figure 4–22. Tx Path Delay to AUX Output and to AxC Interfaces
CPRI MegaCore Function User Guide
tx_dataout
Tx Path Delay
Transceiver
Transmitter
The Rx path delay to output on the AxC interface has the same components
the Rx path delay to the AUX interface. These components comprise the delay from
input to the receiver transceiver on the CPRI link, to input to the MAP interface block.
The delay from there to the individual AxC interfaces is the time the data spends in
the mapN Rx buffer, before being written to the AxC interface data channel. In
synchronous buffer mode, this delay is one cycle if the sample rate is a multiple of
3.84 MHz, and two cycles otherwise. Refer to
page
The Tx path delay is the cumulative delay from the arrival of the first bit of an IQ data
sample on the CPRI AUX interface or on a CPRI AxC interface, to the start of
transmission of this data on the CPRI link.
two Tx paths.
In the CPRI MegaCore function the delay from the AUX interface is fixed. This path
has no variable delay component, because it does not cross clock domains.
The Tx path delay from the AUX interface comprises the following delays:
1. Fixed delay from the AUX interface through the CPRI low-level transmitter to the
2. Link delay through the transceiver. This delay is T_txv_TX in
The Tx path delay from an AxC interface comprises the following delays:
1. Delay through the mapN Tx buffer.
2. Fixed delay from the mapN Tx buffer through the CPRI low-level transmitter to
3. Link delay through the transceiver.
transceiver. This delay is T_T4 in
page
the transceiver.
4–29.
4–42.
Physical Layer
Transmitter
AUX Interface
Module
AUX
Table 4–8 on page
Interface Module
CPRI MAP
Figure 4–22
“CPRI MAP Receiver Interface” on
AxC IF 0
AxC IF n
shows the relation between the
4–44.
December 2010 Altera Corporation
Chapter 4: Functional Description
Table 4–6 on
Data Channels
Delay Measurement
1
and
2
as