IP-CPRI Altera, IP-CPRI Datasheet - Page 76

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–52
MII Interface to an External Ethernet Block
CPRI MegaCore Function User Guide
MII Interface Transmitter
Table 4–9. HDLC Channel Bit Rates (Part 2 of 2)
The HDLC channel rate is determined during the software set-up sequence or by
dynamic modification, in which the same new pointer value is received in CPRI
control byte Z.66.0 four hyperframes in a row. The accepted receive rate is specified in
the rx_slow_cm_rate field of the CPRI_CM_STATUS register, and the transmit rate is
specified in the tx_slow_cm_rate field of the CPRI_CM_CONFIG register.
The CPU interface control for the HDLC channel is identical to the CPU interface
control for the Ethernet channel, with the following exceptions:
■
■
■
You can define a CPRI MegaCore function to bypass the internal Ethernet or HDLC
module and communicate directly with an external Ethernet block through an
MII-like interface, referred to in this document as the MII interface. This interface is
not a true MII interface, because it is clocked by the cpri_clkout clock (which drives
the cpri_mii_txclk and cpri_mii_rxclk clock signals directly), whose frequencies do
not match the usual 2.5 MHz and 25 MHz frequencies of an MII interface. If you use
this interface, your external Ethernet block must communicate with the CPRI
MegaCore function synchronously with the cpri_mii_txclk and cpri_mii_rxclk
clocks.
The MII interface supports the bandwidth described in the CPRI V4.1 Specification in
Table 12, Achievable Ethernet bit rates.
The MII interface transmitter module receives data from the external Ethernet MAC
block and writes it to the CPRI transmitter module, which transmits it on the CPRI
link. It performs 4B/5B encoding on the incoming data nibbles before sending them to
the CPRI transmitter module.
After the CPRI MegaCore function achieves frame synchronization, the MII interface
transmitter module can accept incoming data on the MII interface. The MII interface
transmitter module asserts the cpri_mii_txrd signal to indicate it is ready to accept
data from the external Ethernet MAC block. After the cpri_mii_txrd signal is
asserted, the external Ethernet block asserts the cpri_mii_txen signal to indicate it is
Note to
(1) When Z.66.0.0[2:0] holds value 3’b111, the HDLC bit rate is the highest HDLC bit rate possible for the current CPRI
HDLC register names replace ETH with HDLC
HDLC channel control has fewer configurations than the Ethernet channel control
HDLC channel control does not support address filtering
line rate. You can derive that bit rate from the other entries in this table.
Value in Z.66.0.0[2:0]
Table
4–9:
110
111
HDLC Bit Rate
(Kbps)
3840
4800
MII Interface to an External Ethernet Block
(1)
December 2010 Altera Corporation
Chapter 4: Functional Description
Minimum CPRI Line Rate
(Mbps)
4915.2
6144.0