IP-CPRI Altera, IP-CPRI Datasheet - Page 36

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–12
Figure 4–7. CPRI MegaCore Function Master Clocking at CPRI Line Rate 0.6144 Gbps
Table 4–1. CPRI Link Line Rates and Clock Rates for CPRI MegaCore Function (Part 1 of 2)
CPRI MegaCore Function User Guide
gxb_txdataout
Line Rate
gxb_rxdatain
(Mbps)
1228.8
614.4
CPRI Communication Link Line Rates
gxb_refclk
Stratix IV GX
In Arria II GZ
pll_inclk
Devices
61.44
61.44
and
ALTGX
Figure 4–7
REC or as an RE master with CPRI line rate 0.6144 Gbps in an Arria II GX, Arria II GZ,
Cyclone IV GX, or Stratix IV GX device.
CDR
The CPRI specification specifies line rates of n × 614.4 Mbps for n = 1 to n = 10. The
CPRI MegaCore function implements line rates of n × 614.4 Mbps for n in
{1,2,4,5,8,10}. Cyclone IV GX devices support line rates of n × 614.4 Mbps only for n in
{1,2,4,5}.
reference clock (gxb_refclk) rates, parallel recovered clock (pll_clkout) rates, and
internal clock (cpri_clkout) rates.
Default gxb_refclk Frequency
rx_clkout
tx_clkout
In Arria II GX Devices
Table 4–1
shows the clock diagram for a CPRI MegaCore function configured as an
data
gxb_pll_inclk
61.44
61.44
8
8
shows the relationship between line rates, default transceiver
data
Divide
Divide
by 4
by 4
FIFO
FIFO
In Cyclone IV GX
Clock Frequency (MHz)
Devices
61.44
61.44
32
cpri_clkout
data
32
clk_ex_delay
Sync Buffer
CPRI RX
Rx Elastic
CPRI TX
is supported)
clk
clk
cpri_clkout
(If line rate
Frequency
cpri_tx_aux_data
32
30.72
15.36
32
cpri_rx_aux_data
32
32
Ethernet MAC
data
HDLC
CPRI MegaCore Function
clk
clk
data
Cyclone IV GX
In Arria II GX
December 2010 Altera Corporation
Chapter 4: Functional Description
(If line rate is supported)
Devices
61.44
pll_clkout Frequency
61.44
CPRI Tx
Interface
CPRI Rx
Interface
and
FIFO
FIFO
MAP
MAP
Clocking and Reset Structure
clk
MII Interface
Interface
CPU
mapXX_tx_data
mapXX_tx_clk
mapXX_rx_clk
mapXX_rx_data
Stratix IV GX
In Arria II GZ
Devices
61.44
30.72
and
cpri_mii_txclk
cpri_mii_rxclk
cpu_clk
cpu_writedata
cpu_readdata