IP-CPRI Altera, IP-CPRI Datasheet - Page 67

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Delay Measurement
Table 4–7. Resolution as a Function of M/N Ratio at 3072 Mbps on a Stratix IV GX Device
December 2010 Altera Corporation
Note to
(1)
(2)
Table 4–1 on page 4–12
“CPRI Receive Buffer Delay Calculation Example”
cpri_clkout period.
128
64
M
1
Table
4–7:
127
63
N
4
number M of cpri_clkout periods. For example, N may be a multiple of M, or the
M/N frequency ratio may be slightly greater than 1, such as 64/63 or 128/127. The
application layer specifies N to ensure the accuracy your application requires. The
accuracy of the Rx buffer delay measurement is N/least_common_multiple(N,M)
cpri_clkout periods.
The rx_buf_delay field of the CPRI_RX_DELAY register indicates the number of 32-bit
words currently in the Rx buffer. After you program the rx_ex_delay field of the
CPRI_EX_DELAY_CONFIG register with the value of N, the rx_ex_buf_delay field of the
CPRI_EX_DELAY_STATUS register holds the current measured delay through the Rx
buffer. The unit of measurement is cpri_clkout periods. The rx_ex_buf_delay_valid
field indicates that a new measurement has been written to the rx_ex_buf_delay field
since the previous register read. The following sections explain how you set and use
these register values to derive the extended Rx delay measurement information.
M/N Ratio Selection
As your selected M/N ratio approaches 1, the accuracy provided by the use of the
clk_ex_delay clock increases.
resolutions they provide, for a CPRI MegaCore function that runs at data rate
3072 Mbps and targets a Stratix IV GX device.
CPRI Receive Buffer Delay Calculation Example
This section walks you through an example that shows you how to calculate the
frequency at which to run clk_ex_delay, and how to program and use the registers to
determine the delay through the CPRI Receive buffer.
For example, assume your CPRI MegaCore function runs at data rate 3072 Mbps. In
this case,
so a cpri_clkout cycle is 1/(76.80 MHz).
Refer to
your accuracy resolution requirements are satisfied by an M/N ratio of 128/127,
follow these steps:
1. Program the value N=127 in the rx_ex_delay field of the CPRI_EX_DELAY_CONFIG
lists the cpri_clkout frequency for each CPRI data rate and device family.
register at offset 0x3C
Table 4–7
Table 4–1 on page 4–12
cpri_clkout Period
(1/76.80 MHz)
13.02 ns
for the accuracy resolution provided by some sample M/N ratios. If
shows you how to calculate the clk_ex_delay clock period for a given M, N, and
(Table 6–19 on page
(1)
Table 4–7
shows that the cpri_clkout frequency is 76.80 MHz,
clk_ex_delay Period
shows some example M/N ratios and the
13.12 ns
13.22 ns
3.25 ns
6–9).
(2)
CPRI MegaCore Function User Guide
Resolution
±3.25 ns
±100 ps
±200 ps
4–43