IP-CPRI Altera, IP-CPRI Datasheet - Page 44

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–20
CPRI MegaCore Function User Guide
Figure 4–10. CPRI Frame Synchronization Machine
Note for
(1) LOS=1 returns the state machine to the XACQ1 state. This transition has highest priority.
Recording the Incoming Control Bytes
A control receive table contains a 1-byte entry for each of the 256 control words in the
current hyperframe. The control receive table entries are updated only when the
frame synchronization state machine is in the HFNSYNC state, in which hyperframe
synchronization has been performed successfully. To read a control byte, write the
frame number X to the CPRI_CTRL_INDEX register and then read the last received
#Z.X.0 control byte in the CPRI_RX_CTRL register.
Received K28.5 Byte/
Received K28.5 Byte
Received K28.5 Byte
Received K28.5 Byte
Received K28.5 Byte
Set Y:=W:=X:=0
Figure
and LOS=0
and LOS=0
and LOS=0
and LOS=0
Y=W=X=0
Y=W=X=0
Y=W=X=0
Y=W=X=0
4–10:
Received K28.5 Byte
and
and
and
and
and LOS=0
Y=W=X=0
and
Power Up or Reset
HFNSYNC
XSYNC1
XSYNC2
XSYNC3
XACQ1
XACQ2
Received Byte
Not K28.5
Received Byte
Not K28.5
LOS=1
(Note 1)
Received Byte
Not K28.5
Received Byte
Not K28.5
Received Byte
Not K28.5
December 2010 Altera Corporation
Chapter 4: Functional Description
Physical Layer
LOF=1
LOF=0