IP-CPRI Altera, IP-CPRI Datasheet - Page 83

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Signals
Physical Layer Signals
Table 5–6. Transceiver Signals (Part 1 of 2)
December 2010 Altera Corporation
gxb_cal_blk_clk
gxb_pll_inclk
reconfig_clk
reconfig_togxb_s_tx
[3:0]
reconfig_togxb_s_rx
[3:0]
reconfig_togxb_m[3:0]
reconfig_fromgxb_s_tx
[16:0] ([4:0] for
Cyclone IV GX devices)
reconfig_fromgxb_s_rx
[16:0] ([4:0] for
Cyclone IV GX devices)
reconfig_fromgxb_m
[16:0] ([4:0] for
Cyclone IV GX devices)
reconfig_busy
(1)
(1)
Transceiver Signals
Signal
(1)
Table 5–6
block. In many cases these signals must be shared by multiple transceiver blocks that
are implemented in the same device
(1)
lists the transceiver signals that are connected directly to the transceiver
Direction
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
The Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX transceivers’
on-chip termination resistors are calibrated by a single calibration block.
This circuitry requires a calibration clock. The frequency range of the
gxb_cal_blk_clk is 10–125 MHz. For more information, refer to the
Transceiver Architecture for Arria II Devices
Arria II Device Handbook, the
in volume 2 of the Cyclone IV Device Handbook, or the
Architecture
Input clock to the transceiver PLL. If the CPRI MegaCore function is
configured in master clocking mode, it does not use this clock. In master
clocking mode, you must tie this input to 0.
In slave clocking mode, the gxb_pll_inclk signal connects directly to the
rx_cruclk input signal of the transceiver’s PLL.
Reference clock for the dynamic reconfiguration controller. The frequency
range for this clock is 37.5–50 MHz.
Driven from an external dynamic reconfiguration block to the slave
transmitter transceiver block. Supports the selection of multiple transceiver
channels for dynamic reconfiguration.
Driven from an external dynamic reconfiguration block to the slave receiver
transceiver block. Supports the selection of multiple transceiver channels
for dynamic reconfiguration.
Driven from an external dynamic reconfiguration block to the master
transceiver block. Supports the selection of multiple transceiver channels
for dynamic reconfiguration.
Driven to an external dynamic reconfiguration block from the slave
transmitter transceiver block. The bus identifies the transceiver channel
whose settings are being transmitted to the dynamic reconfiguration block.
Driven to an external dynamic reconfiguration block from the slave receiver
transceiver block. The bus identifies the transceiver channel whose settings
are being transmitted to the dynamic reconfiguration block.
Driven to an external dynamic reconfiguration block from the master
transceiver block. The bus identifies the transceiver channel whose settings
are being transmitted to the dynamic reconfiguration block.
Indicates the busy status of the dynamic reconfiguration controller. After the
device powers up, this signal remains low for the first reconfig_clk clock
cycle. It is then asserted and remains high while the dynamic
reconfiguration controller performs offset cancellation on all the receiver
channels connected to the ALTGX_RECONFIG instance. This signal is
deasserted when offset cancellation completes successfully.
chapter in volume 2 of the Stratix IV Device Handbook.
Cyclone IV Transceivers Architecture
Description
chapter in volume 2 of the
CPRI MegaCore Function User Guide
Stratix IV Transceiver
chapter
5–3