IP-CPRI Altera, IP-CPRI Datasheet - Page 51

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
CPRI MAP Interface Module
December 2010 Altera Corporation
AxC containers are packed in the IQ data block in a flexible position (Option 2), as
illustrated in Section 4.2.7.2.3 of the CPRI V4.1 Specification. Configuration tables
define the mapping of AxC containers to offsets in the AxC interface timeslots.
The CPRI MegaCore function supports the following two advanced AxC mapping
modes:
■
■
Both of the advanced AxC mapping modes comply with the description in Section
4.2.7.2.4 of the CPRI V4.1 Specification.
You specify the flexible position of the start of an AxC container in its timeslot using
the Rx and Tx mapping tables. You configure the Rx and Tx mapping tables through
the CPU interface. You can configure one mapping table entry at a time. The table
index specified in the map_conf_index field of the CPRI_MAP_TBL_INDEX register
determines the Rx and Tx mapping table entries that appear in the CPRI_MAP_TBL_RX
and CPRI_MAP_TBL_TX registers, respectively.The CPRI_MAP_TBL_RX register holds the
currently configurable entry in the Rx mapping table, and the CPRI_MAP_TBL_TX
register holds the currently configurable entry in the Tx mapping table.
Each table entry corresponds to a timeslot, which is a 32-bit word on the AxC
interface, in one AxC container block. In 16-bit width mode, a timeslot corresponds to
as many as 32 bits of data. In 15-bit width mode, a timeslot corresponds to 30 bits of
data. Each table entry has an enable bit and a field in which to specify the AxC
interface number for the current timeslot, in addition to a position field which
specifies the starting bit position of the IQ sample in the timeslot. The application can
specify an offset for the start of an AxC container in a timeslot; the position field of
the table entry that corresponds to the timeslot in which that AxC container begins
transmission (in the CPRI Rx direction) or appears on the data channel (in the CPRI Tx
direction), holds this offset. The offset is specified in bits. The position field is
ignored in 15-bit width mode. You cannot specify an offset in 15-bit width mode.
You can calculate the number of timeslots that correspond to a CPRI frame. Only the
data bytes pass through the AxC interface; the control bytes in a CPRI frame do not
pass through the AxC interface. Refer to the leftmost column of
page 4–25
columns are the numbers of data bits in a CPRI frame at each CPRI line data rate. The
calculation depends on the presence and values of any offsets, on whether the CPRI
MegaCore function is in 15-bit width mode or in 16-bit width mode, and on how
remainder bytes are handled. The following discussion focuses on the cases with
offsets all set to zero. You can increment the timeslot counts as needed to
accommodate the unused leading timeslot bits specified with offsets.
In 16-bit width mode, the two advanced AxC mapping modes differ in how they
handle spare bytes in the CPRI frame. In 15-bit width mode, the two advanced AxC
mapping modes act identically. Because the number of bits in the IQ data block of
every CPRI frame is a multiple of 30, packed 15-bit I- and Q-samples fill an AxC
container—and one or more CPRI frames—with no spare bytes remaining.
When map_mode has value 2’b01, AxC mapping conforms to Method 1: IQ Sample
Based, described in Section 4.2.7.2.5 of the CPRI V4.1 Specification.
When map_mode has value 2’b10, AxC mapping conforms to Method 3: Backward
Compatible, described in Section 4.2.7.2.7 of the CPRI V4.1 Specification.
or
Table 4–5 on page
4–26. The numbers in square brackets in those
CPRI MegaCore Function User Guide
Table 4–4 on
4–27