IP-CPRI Altera, IP-CPRI Datasheet - Page 115

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Software Interface
Ethernet Registers
Ethernet Registers
Table 6–48. CPRI Ethernet Registers Memory Map
Table 6–49. ETH_RX_STATUS—Ethernet Receiver Module Status—Offset: 0x200
December 2010 Altera Corporation
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
0x238–0x240
0x244
0x248
0x24C
RSRV
rx_ready_block
rx_ready_end
rx_length
rx_abort
rx_eop
rx_ready
Address
Field
This section lists the Ethernet registers.
Ethernet registers.
CPRI MegaCore function.
[31:7] UR0
[6]
[5]
[4:3]
[2]
[1]
[0]
Bits
ETH_RX_STATUS
ETH_TX_STATUS
ETH_CONFIG_1
ETH_CONFIG_2
ETH_RX_CONTROL
ETH_RX_DATA
ETH_RX_DATA_WAIT
ETH_TX_CONTROL
ETH_TX_DATA
ETH_TX_DATA_WAIT
Reserved
ETH_MAC_ADDR_MSB
ETH_MAC_ADDR_LSB
ETH_HASH_TABLE
Reserved
ETH_FWD_CONFIG
ETH_CNT_RX_FRAME
ETH_CNT_TX_FRAME
RO
RO
RO
RO
RO
RO
Access
Name
Reserved.
Indicates that an 8-word block of Ethernet data is available to be
transmitted on the Ethernet channel.
Indicates the end-of-packet (EOP) is available in the Ethernet Rx
buffer, ready to be transmitted on the Ethernet channel.
Length of the final word in the packet. Values are:
Indicates the current Ethernet Rx packet is aborted.
Indicates that the next ready data word contains the end-of-packet
byte.
Indicates that at least one 32-bit word of Ethernet data is available in
the Ethernet Rx buffer and ready to be read.
00: 1 valid byte
01: 2 valid bytes
10: 3 valid bytes
11: 4 valid bytes
Table 6–49
through
Ethernet Receiver Module Status
Ethernet Transmitter Module Status
Ethernet Feature Configuration 1
Ethernet Feature Configuration 2
Ethernet Rx Control
Ethernet Rx Data
Ethernet Rx Data With Wait-State Insertion
Ethernet Tx Control
Ethernet Tx Data
Ethernet Tx Data With Wait-State Insertion
Ethernet MAC Address MSB (16 bits)
Ethernet MAC Address LSB (32 bits)
Ethernet Multicast Filtering Hash Table
Ethernet Forwarding Configuration
Ethernet Receiver Module Frame Counter
Ethernet Transmitter Module Frame Counter
Table 6–64
Table 6–48
Function
describe the Ethernet registers in the
provides a memory map for the
Expanded Name
CPRI MegaCore Function User Guide
25'h0
1’h0
1’h0
2’h0
1’h0
1’h0
1’h0
Default
6–19