IP-CPRI Altera, IP-CPRI Datasheet - Page 140

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–4
CPRI MegaCore Function User Guide
2. Set the logic that feeds the gxb_refclk input to the CPRI MegaCore function to the
3. Configure the ALTGX_RECONFIG megafunction with the .mif file for the desired
4. For a Cyclone IV GX device, configure the ALTPLL_RECONFIG megafunction
5. Set the i_datarate_set field of the AUTO_RATE_CONFIG register to the correct value
6. Confirm the field is set by monitoring the datarate_set output signal.
7. Optionally, to enable confirmation of frame synchronization at the new CPRI line
8. If you reset the tx_enable bit of the CPRI_CONFIG register in step 7, after
correct value for the next CPRI line rate at which you want to try to achieve frame
synchronization.
CPRI line rate.
with the .mif file for the desired CPRI line rate, by performing the following steps:
a. Assert the write_from_rom input signal to the ALTPLL_RECONFIG megafunction.
b. After the megafunction busy output signal is deasserted, assert the
c. After the CPRI MegaCore function pll_reconfig_done signal is deasserted,
for the next CPRI line rate at which you want to try to achieve frame
synchronization.
rate, reset the tx_enable bit of the CPRI_CONFIG register to 0.
The frame synchronization machine shown in
to achieve frame synchronization at the specified CPRI line rate.
extended_rx_status_data[1:0] changes value to 0x1, set the tx_enable bit of the
CPRI_CONFIG register.
The value 0x3 on the extended_rx_status_data[1:0] signal confirms that the
CPRI receiver has achieved frame synchronization.
The megafunction busy output signal is asserted and remains asserted while
the megafunction writes to the scan cache.
megafunction reconfig signal. While PLL reconfiguration is in progress, the
busy signal is again asserted.
assert the megafunction reset_rom_address signal.
Appendix B: Implementing CPRI Link Auto-Rate Negotiation
Figure 4–10 on page 4–20
December 2010 Altera Corporation
Running Auto-Rate Negotiation
attempts