IP-CPRI Altera, IP-CPRI Datasheet - Page 133

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IP-CPRI

Manufacturer Part Number
IP-CPRI
Description
IP CORE - Common Public Radio Interface (CPRI)
Manufacturer
Altera
Datasheets

Specifications of IP-CPRI

Software Application
IP CORE, Interface And Protocols, HIGH SPEED
Supported Families
Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
Chapter 7: Testbenches
Running the Testbenches
December 2010 Altera Corporation
8. To compile and run the appropriate testbench for the DUT you generated in step 1,
The input to and subsequent output data from each of the AUX, map0, and MII
interfaces is visible in the waveform for testbenches that have the relevant interface.
using the ModelSim simulator, type the following command:
do compile[_<variation>]_<HDL>.do r
To prepare to simulate VHDL files with ModelSim SE, perform the following
edits:
To prepare to simulate Verilog HDL files with ModelSim SE, perform the
following edits:
Change all instances of src/cpri_top_level.vho to
../../cpri_top_level_sim/cpri_top_level.vho.
Change all instances of test/tb_altera_cpri[_<variation>].vhd to
tb_altera_cpri[_<variation>].vhd.
For the auto-rate negotiation testbenches, change all remaining instances of
src/<file>.vhd to <file>.vhd.
Change all instances of src/cpri_top_level.v to
../../cpri_top_level_sim/cpri_top_level.v.
Change all instances of test/tb_altera_cpri[_<variation>].v to
tb_altera_cpri[_<variation>].v.
For the auto-rate negotiation testbenches, change all remaining instances of
src/<file>.v to <file>.v.
CPRI MegaCore Function User Guide
7–9

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