IP-CPRI Altera, IP-CPRI Datasheet - Page 29

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Clocking and Reset Structure
December 2010 Altera Corporation
High-Speed Transceiver Clocks
MII Interface Clock Domains
f
The cpri_clkout and cpu_clk clocks are assumed to be asynchronous. The cpu_clk
maximum value is constrained by f
grade.
The following input clocks are used by the high-speed transceiver on the CPRI
MegaCore function CPRI interface:
■
■
■
■
In slave clocking mode, the gxb_pll_inclk clock connects to the pll_inclk input
signal of the Arria II GX, Arria II GZ, or Stratix IV GX transceiver’s PLL, and the
gxb_refclk clock connects to the rx_cruclk input signal of the transceiver. In master
clocking mode, the CPRI MegaCore function connects the gxb_refclk clock to the
pll_inclk input signal of the transceiver, and does not use the gxb_pll_inclk input
signal. Refer to
In master clocking mode, the two transceiver signals pll_inclk and rx_cruclk are
implemented as a single input signal to the ALTGX megafunction, named
pll_inclk_rx_cruclk. However, the clocking mode implementation ensures that the
CPRI MegaCore function signal is interpreted correctly.
For more information about the high-speed transceiver blocks, refer to
Arria II Device Handbook, to
and
The MII interface has the following two output clocks:
■
■
Both clocks have the same frequency as the cpri_clkout clock. The frequency
depends on the CPRI line data rate. Refer to
gxb_refclk—Reference clock for the transceiver PLLs. In master clocking mode,
this clock drives both the receiver PLL and the transmitter PLL in the transceiver.
In slave clocking mode, this clock drives the receiver PLL.
gxb_cal_blk_clk—Calibration-block clock.
reconfig_clk—Dynamic reconfiguration block clock.
gxb_pll_inclk—Input clock to the transmitter PLL in a CPRI MegaCore function
configured in slave clocking mode. If the CPRI MegaCore function is configured in
master clocking mode, it does not use this clock. In master clocking mode, you
must tie this input to 0.
cpri_mii_txclk—Clocks the MII interface transmitter module.
cpri_mii_rxclk—Clocks the MII interface receiver module.
volume 3
of the Stratix IV Device Handbook.
“Clock Diagrams for the CPRI MegaCore Function” on page
volume 2
MAX
of the Cyclone IV Device Handbook, or to
and can vary based on the family and speed
Table 4–1 on page
CPRI MegaCore Function User Guide
4–12.
volume 2
volume 2
4–6.
of the
4–5