IP-CPRI Altera, IP-CPRI Datasheet
IP-CPRI
Specifications of IP-CPRI
Related parts for IP-CPRI
IP-CPRI Summary of contents
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... CPRI MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01062-3.0 CPRI MegaCore Function Document last updated for Altera Complete Design Suite version: Document publication date: User Guide 10.1 December 2010 Subscribe ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... MegaWizard Plug-in Manager Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Specify Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Compile and Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Instantiate Multiple CPRI MegaCore Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Chapter 3. Parameter Settings Line Rate Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Operation Mode Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Transceiver Starting Channel Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Number of Antenna-Carrier Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3– ...
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... Tx Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–46 T14, Toffset, Round-Trip Delay, and Round-Trip Cable Delay Calculations . . . . . . . . . . . . . . . . . . 4–47 Round-Trip and Cable Delay Calculations for a Single-Hop Configuration . . . . . . . . . . . . . . . . 4–47 Round-Trip Calculations for a Multi-Hop Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–48 Data Link Layer for Fast Control and Management Channel (Ethernet 4–49 Ethernet Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–49 Ethernet Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4– ...
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... Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1 Configuring the CPRI MegaCore Function for Auto-Rate Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . B–3 Running Auto-Rate Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3 Additional Information Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2 December 2010 Altera Corporation v CPRI MegaCore Function User Guide ...
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... CPRI MegaCore Function User Guide Contents December 2010 Altera Corporation ...
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... The Altera CPRI MegaCore Interface (CPRI) specification. CPRI is a high-speed serial interface designed for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE). The CPRI MegaCore function targets high-performance, remote, radio network applications. You can configure the CPRI MegaCore function REC. ...
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... Note to Figure 1–2: (1) You can configure your CPRI MegaCore function with zero, one, or multiple antenna-carrier interfaces. (2) You can configure your CPRI MegaCore function with an Ethernet MAC block or an MII block. CPRI MegaCore Function Features The CPRI MegaCore function has the following features: Compliant with ■ ...
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... Chapter 1: About This MegaCore Function CPRI MegaCore Function Features ■ Interface to external or on-chip processor, using the Altera Avalon Memory-Mapped (Avalon-MM) interconnect specification. AUX interface allows you to pass data from slave to master ports or custom ■ mappers to implement daisy-chain topologies. Accurate CPRI connection Rx delay measurement. ...
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... Table 1–1. Altera IP Core Device Support Levels FPGA Device Families Preliminary support—The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution. ...
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... Table 1–3. CPRI MegaCore Function FPGA Resource Utilization (Part Parameters Device Line Rate Include MAC (Mbps) Block Yes 614.4 No Arria II GX Yes 1228.8, 2457.6, 3072, 4915.2, 6144 No Yes Arria II GZ 614.4 No December 2010 Altera Corporation Number of Combinational Antenna-Carrier ALUTs Interfaces 0 4281 1 5580 2 5859 3 6092 4 6342 0 2163 1 3515 2 3794 ...
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... December 2010 Altera Corporation ...
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... CPRI line rate in each device family. Lower speed grade numbers correspond to faster devices. Table 1–5. Slowest Recommended Device Family Speed Grades Device Family 614.4 Arria Arria Cyclone IV GX C8, I7 December 2010 Altera Corporation Parameters Number of Include MAC Antenna-Carrier Block Interfaces 0 1 Yes 2 ...
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... CPRI Line Rate (Mbps) 1228.8 2457.6 3072 Item MegaCore IP Library Release Notes and Chapter 1: About This MegaCore Function Release Information 4915.2 6144 -4 -3 Description 10.1 December 2010 IP-CPRI 00CB 6AF7 Errata. Altera does not verify December 2010 Altera Corporation ...
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... Contains shared components cpri Contains the CPRI MegaCore function files src Contains encrypted lower-level design files constraints Contains the Synopsys Design Constraints script for the MegaCore function cus_demo_tb Contains the demonstration testbench for the MegaCore function www.altera.com/licensing 1–9 and install it on your ...
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... CPRI link and the CPU interface reset. The transceivers do not reset, because the transceiver quad might be shared with other designs, MegaCore functions, and megafunctions. The CPRI MegaCore function cannot achieve frame synchronization, and cannot participate in further CPRI communication. f For Information About ...
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... Specify Parameters To specify CPRI MegaCore function parameters using the MegaWizard Plug-in Manager, follow these steps: 1. Create a Quartus II project using the New Project Wizard available from the File menu. December 2010 Altera Corporation 2. Getting Started MegaWizard Plug-In Manager Flow Specify Parameters Generate ...
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... You might have to wait several minutes for file generation to complete you generate the CPRI MegaCore function instance in a Quartus II project, you are prompted to add the Quartus II IP File (.qip) to the current Quartus II project. You can also turn on Automatically add Quartus II IP Files to all projects. ...
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... MegaCore function variation using the IP functional simulation model and the VHDL demonstration testbench. The IP functional simulation model and testbench files are generated in your project directory. The directory also includes scripts to compile and run the demonstration testbench. The testbench demonstrates how to instantiate a model in a design and includes simple stimuli to control the user interfaces of the CPRI MegaCore function ...
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... ALTGX megafunction) is driven by the same calibration clock source. When you merge multiple CPRI MegaCore functions in a single transceiver block, the same signal must drive gxb_powerdown to each of the CPRI MegaCore function variations and other megafunctions, MegaCore functions, and user logic that use the ALTGX megafunction ...
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... You can specify the starting number for the CPRI MegaCore function transceiver. For a CPRI MegaCore function master, the Master transceiver starting channel number specifies the starting channel number for the transceiver. December 2010 Altera Corporation 3. Parameter Settings CPRI MegaCore Function User Guide ...
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... Both numbers must be starting channel numbers available in your design. The two numbers must be different but the Quartus II software creates an FPGA configuration with a single slave transceiver. If you instantiate multiple CPRI MegaCore functions on the same device, you must ensure each uses distinct transceiver channels. Number of Antenna-Carrier Interfaces The Number of antenna/carrier interfaces parameter specifies the number of antenna-carrier interfaces, or data channels, in your CPRI MegaCore function ...
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... For information about the internal Ethernet MAC block, refer to Fast Control and Management Channel (Ethernet)” on page For information about the MII interface, refer to Block” on page December 2010 Altera Corporation and Appendix B, Implementing CPRI Link Auto-Rate “MII Interface to an External Ethernet 4– ...
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... CPRI MegaCore Function User Guide Chapter 3: Parameter Settings Include MAC Block December 2010 Altera Corporation ...
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... Data Link Layer for Fast Control and Management Channel (Ethernet) ■ Data Link Layer for Slow Control and Management Channel (HDLC) ■ MII Interface to an External Ethernet Block December 2010 Altera Corporation 4. Functional Description CPRI MegaCore Function User Guide ...
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... Note to Figure 4–1: (1) You can configure your CPRI MegaCore function with zero, one, or multiple IQ data channels. (2) You can configure your CPRI MegaCore function with an Ethernet MAC block or an MII block. The following sections describe the individual interfaces and clocks. Interfaces Overview ...
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... CPU interface. Use this interface to communicate Control and Management (C&M) information and for High-Level Data Link Controller (HDLC) or Ethernet communication with an internal MAC block. An on-chip processor such as the Nios II processor external processor, can access the CPRI configuration address space using this interface. The CPRI MegaCore function does not implement arbitration among the modules that connect to it through the CPU interface ...
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... CPRI MegaCore Function User Guide “Auxiliary Interfaces” on page 4–33. 4–52. “Architecture Overview” on page 4–2 Figure 4–2 on page 4–7 4–12. “Extended Rx Delay Measurement” on page Chapter 4: Functional Description Clocking and Reset Structure Avalon Interface Specifications. “MII define the clock to Figure 4–5 on “ ...
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... Chapter 4: Functional Description Clocking and Reset Structure The cpri_clkout and cpu_clk clocks are assumed to be asynchronous. The cpu_clk maximum value is constrained by f grade. High-Speed Transceiver Clocks The following input clocks are used by the high-speed transceiver on the CPRI MegaCore function CPRI interface: ■ ...
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... CPRI MegaCore Function User Guide 4–26. Figure 4–5 show the clocking schemes for CPRI MegaCore functions Figure 4–6 and Figure 4–7 show the clock diagrams for CPRI MegaCore Chapter 4: Functional Description Clocking and Reset Structure Table 4–4 and December 2010 Altera Corporation ...
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... Chapter 4: Functional Description Clocking and Reset Structure Figure 4–2 shows the clock diagram for a CPRI MegaCore function configured slave with CPRI line rate greater than 0.6144 Gbps in an Arria Cyclone IV GX device. Figure 4–2. CPRI MegaCore Function Slave Clocking in Arria II GX and Cyclone IV GX Devices ...
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... CPRI TX Divide by 2 clk data 16 32 data clk FIFO CPRI RX Divide Elastic Sync Buffer gxb_pll_inclk clk_ex_delay Chapter 4: Functional Description Clocking and Reset Structure CPRI MegaCore Function CPRI Tx MAP mapXX_tx_data 32 data Interface FIFO mapXX_tx_clk cpri_mii_txclk MII Interface cpri_mii_rxclk Ethernet MAC clk cpu_clk ...
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... Chapter 4: Functional Description Clocking and Reset Structure Figure 4–4 shows the clock diagram for a CPRI MegaCore function configured slave with CPRI line rate greater than 0.6144 Gbps in an Arria Stratix IV GX device. Figure 4–4. CPRI MegaCore Function Slave Clocking in Arria II GZ and Stratix IV GX Devices ...
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... CPRI TX tx_clkout clk 32 data clk CPRI RX rx_clkout Rx Elastic 32 Sync Buffer 32 gxb_pll_inclk clk_ex_delay cpri_rx_aux_data Chapter 4: Functional Description Clocking and Reset Structure CPRI MegaCore Function CPRI Tx MAP mapXX_tx_data 32 data Interface FIFO mapXX_tx_clk cpri_mii_txclk MII Interface cpri_mii_rxclk Ethernet MAC clk cpu_clk clk ...
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... Chapter 4: Functional Description Clocking and Reset Structure Figure 4–6 shows the clock diagram for a CPRI MegaCore function configured slave with CPRI line rate 0.6144 Gbps in an Arria II GX, Arria II GZ, Cyclone IV GX, or Stratix IV GX device. Figure 4–6. CPRI MegaCore Function Slave Clocking at CPRI Line Rate 0.6144 Gbps ...
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... FIFO CPRI RX Divide Elastic Sync Buffer gxb_pll_inclk clk_ex_delay shows the relationship between line rates, default transceiver Clock Frequency (MHz) cpri_clkout Frequency (If line rate In Cyclone supported) Devices 61.44 61.44 61.44 61.44 Chapter 4: Functional Description Clocking and Reset Structure ...
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... CPRI MegaCore function line rate. The ALTGX parameter editor lets you select one of the supported frequencies. MegaCore Function Reset Process The CPRI MegaCore function has multiple independent reset signals. To reset the CPRI MegaCore function completely, you must assert all the reset signals. December 2010 Altera Corporation ...
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... Resets the CPU interface cpu_clk Resets the MAP Channel N receiver block mapN_rx_clk Resets the MAP Channel N transmitter block mapN_tx_clk rst V CC rst rst clk Chapter 4: Functional Description Clocking and Reset Structure Figure 4–8 CPRI MegaCore Function reset Chapter 5, December 2010 Altera Corporation ...
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... Chapter 4: Functional Description Clocking and Reset Structure Reset Control Word Communicated on CPRI Link In addition, a CPRI MegaCore function can receive or send a reset request through the CPRI link. You use the CPRI MegaCore function CPRI_HW_RESET register, and optionally the hw_reset_assert input signal, to control and monitor the reset control word sent in CPRI communication ...
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... Physical Layer The Physical layer of the CPRI protocol is also called Layer 1. This layer controls the electrical characteristics of the CPRI link, the time-division multiplexing of the separate information flows in the protocol, and low-level signaling. The CPRI interface module of the CPRI MegaCore function incorporates Altera’s high-speed transceivers to implement Layer 1 ...
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... Chapter 4: Functional Description Physical Layer Features The Physical layer has the following features: ■ Frame synchronization ■ Transmitter and receiver with the following features: High-speed data serialization and deserialization ■ Clock and data recovery (receiver) ■ 8B/10B encoding and decoding ■ ...
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... The transceiver is an embedded ALTGX megafunction in the Arria II GX, Arria II GZ, Cyclone IV GX, or Stratix IV GX device. The transceiver receiver implements 8B/10B decoding and the deterministic latency protocol. The deterministic latency protocol is designed to meet the 16.276 ns round-trip delay measurement accuracy requirements R21 and R21A of the CPRI specification. Rx Elastic Buffer ...
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... Chapter 4: Functional Description Physical Layer You must realign and resynchronize the Rx elastic buffer after a dynamic CPRI line rate change. Because resynchronizing the Rx elastic buffer resets its pointers, you must ensure that the Rx elastic buffer is empty before it is resynchronized. Program the CPRI_RX_DELAY_CTRL register to realign and resynchronize the Rx elastic buffer. ...
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... Received Byte Not K28.5 XSYNC1 and XSYNC2 and XSYNC3 and HFNSYNC Received K28.5 Byte and Y=W=X=0 and LOS=0 Chapter 4: Functional Description Physical Layer LOF=1 Received Byte Not K28.5 Received Byte Not K28.5 LOF=0 Received Byte Not K28.5 December 2010 Altera Corporation ...
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... Chapter 4: Functional Description Physical Layer Auto-Rate Negotiation The auto-rate negotiation feature allows the CPRI MegaCore function to determine the CPRI line rate at startup dynamically, by stepping down to successively slower line rates if the low-level receiver cannot achieve frame synchronization with the current line rate. If you enable the auto-rate negotiation feature, you can provide dynamic input to the low-level CPRI interface receiver to implement this capability in your design, using logic you implement outside the MegaCore function ...
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... Arria Stratix IV GX transmitter, to 8-bit data before 8B/10B encoding. The 10-bit encoded data is then serialized and sent to the CPRI link differential output pins. The deterministic latency protocol is designed to meet the 16.276 ns round-trip delay measurement accuracy requirements R21 and R21A of the CPRI specification. CPU Interface Module The CPU interface module provides an Avalon-MM slave interface that accesses all registers in the CPRI MegaCore function ...
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... Chapter 4: Functional Description CPRI MAP Interface Module This section contains the following topics: ■ MAP Interface Mapping Modes CPRI MAP Receiver Interface ■ ■ CPRI MAP Transmitter Interface ■ PRBS Generation and Validation MAP Interface Mapping Modes The map_mode field of the CPRI_MAP_CONFIG register determines the mapping mode implemented by your CPRI MegaCore function ...
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... AxC containers map to the individual active AxC Container ... Container 2 map_ac AxC AxC Interface Interface ... 0 1 Data Data ... ... Figure 4–12 shows the bit correspondence for both sample Chapter 4: Functional Description CPRI MAP Interface Module AxC Reserved Bits AxC Interface map_ac Data ... ... December 2010 Altera Corporation ...
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... Chapter 4: Functional Description CPRI MAP Interface Module Figure 4–12. Bit Correspondence Between IQ Sample and 32-Bit Avalon-ST Data 16-Bit Width IQ Sample Avalon-ST Data Word in AxC Container: 31 15-Bit Width IQ Sample You set the oversampling factor to match the frequency of your active data channels. The CPRI line rate determines the number of bits in the IQ data block of each basic frame ...
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... In the advanced AxC mapping modes, implemented when map_mode has value 2’b01 or 2b’10, different data channels can use different sample rates, and the sample rates need not be integer multiples of 3.84 MHz. However, all data channels use the same sample width. CPRI MegaCore Function User Guide Chapter 4: Functional Description 2 ...
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... CPRI frame. In 15-bit width mode, the two advanced AxC mapping modes act identically. Because the number of bits in the IQ data block of every CPRI frame is a multiple of 30, packed 15-bit I- and Q-samples fill an AxC container—and one or more CPRI frames—with no spare bytes remaining. ...
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... Figure 4–13. Example of Difference Between Two AxC Advanced Mapping Modes map_mode = 2’b01: Timeslot number: 0 map_mode = 2’b10: Timeslot number: 0 CPRI MegaCore Function User Guide Figure 4–13 illustrates this example. 1 ... 6 7 ... 1 ... 6 7 ... Chapter 4: Functional Description CPRI MAP Interface Module Table 4–4 on page 4–25). 8 ... 13 14 ... 8 ... 13 ... December 2010 Altera Corporation ...
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... When map_mode has value 2’b10, each IQ data sample is considered a different AxC container, for backward compatibility with earlier versions of the CPRI specification. However, multiple consecutive 32-bit words in the same frame may contain data samples from or for the same AxC interface. In other words, data to or from the same AxC interface may appear in consecutive timeslots, even though these IQ data samples are considered individual AxC containers ...
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... In addition to ensuring that application-specific constraints are accommodated, the system can set the CPRI_START_OFFSET_RX register to an offset that lags the desired frame position in the CPRI transmission, in anticipation of the delays from the CPRI Rx interface and through the antenna-carrier interface Rx buffer. For information about these delays, refer to Figure 4– ...
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... Rx buffer. You set the values in the CPRI_START_OFFSET_RX and CPRI_MAP_OFFSET_RX registers to provide the correct timing to compensate for delays through the CPRI MegaCore function. For information about delays in the Rx path through the IP core, refer to Path Delay” on page 1 In synchronous buffer mode, Altera recommends that you use sample rates that are integer multiples of 3 ...
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... In addition to ensuring that application-specific constraints are accommodated, the system can set the CPRI_START_OFFSET_TX register to an offset that precedes the desired frame position in the CPRI transmission, in anticipation of the delays through the antenna-carrier interface Tx buffer and out to the CPRI Tx frame buffer. For information about these delays, refer to Figure 4– ...
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... Tx buffer. You set the values in the CPRI_START_OFFSET_TX and CPRI_MAP_OFFSET_TX registers to provide the correct timing to compensate for delays through the CPRI MegaCore function. For information about delays in the Tx path through the IP core, refer to Path Delay” on page PRBS Generation and Validation ...
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... The output synchronization signals are derived from the CPRI interface frame synchronization machine. Their delay following the frame on the CPRI interface reflects the quantified delay through the CPRI IP core. Refer to page 4–40. These signals are all fields in the aux_rx_status_data bus. For additional ...
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... Chapter 4: Functional Description Auxiliary Interfaces Figure 4–16 shows the relationship between the synchronization pulses and numbers. Figure 4–16. Synchronization Pulses and Numbers on the AUX Interfaces cpri_{rx,tx}_rfp cpri_{rx,tx}_bfn cpri_{rx,tx}_hfp cpri_{rx,tx}_hfn cpri_{rx,tx}_x cpri_{rx,tx}_seq The AUX receiver transmits data on the AUX interface in fixed 32-bit words. The mapping to 32-bit words depends on the CPRI MegaCore function line rate. Figure 4– ...
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... Sequence number on AUX interface 1 2 ... #Z.X.2.0 #Z.X.4.0 ... #Z.X.2.1 #Z.X.4.1 ... #Z.X.3.0 #Z.X.5.0 ... #Z.X.3.1 #Z.X.5.1 ... Sequence number on AUX interface 1 2 ... #Z.X.1.0 #Z.X.2.0 ... #Z.X.1.1 #Z.X.2.1 ... #Z.X.1.2 #Z.X.2.2 ... #Z.X.1.3 #Z.X.2.3 ... Chapter 4: Functional Description Auxiliary Interfaces 7 #Z.X.14.0 #Z.X.14.1 #Z.X.15.0 #Z.X.15.1 15 #Z.X.15.0 #Z.X.15.1 #Z.X.15.2 #Z.X.15.3 December 2010 Altera Corporation ...
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... Chapter 4: Functional Description Auxiliary Interfaces Figure 4–17. AUX Interface Outgoing Data at Different CPRI Line Rates (Part 3072.0 Mbps Line Rate: 0 [31:24]: #Z.X.0.0 (1) #Z.X.0.4 [23:16]: #Z.X.0.1 (1) [15:8]: #Z.X.0.2 (1) [7:0]: #Z.X.0.3 (1) 4915.0 Mbps Line Rate: 0 [31:24]: #Z.X.0.0 (1) #Z.X.0.4 [23:16]: #Z.X.0.1 (1) #Z.X.0.5 [15:8]: #Z.X.0.2 (1) #Z ...
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... CPRI link protocol has been overwritten. ■ cpri_tx_sync_rfp—Synchronization input used in REC master to control the start of a new 10 ms radio frame For information about the relationships between the synchronization pulses and numbers, refer to AUX interface and the CPRI link, refer to CPRI MegaCore Function User Guide ...
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... Requirements R-20 and R-21 extrapolate this requirement to single-hop round-trip delay accuracy. R-20 requires that the accuracy of the round-trip delay, excluding cables, be within ±16.276 ns, and R-21 requires that the round-trip cable delay measurement accuracy be within the same range. Requirement R-21A extrapolates this requirement further, to multi-hop round-trip delay accuracy ...
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... Rx path and on the Tx path to the two SAPs—the AUX interface and the MAP interface—and the deterministic values for transceiver latency and delay through the IP core. They describe the calculation of the round-trip cable delay T14, the Toffset delay, and the round-trip (SAP to SAP) delay in the single-hop and multi-hop cases. ...
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... Chapter 4: Functional Description Delay Measurement AUX interface or to output on the MAP interface. between the two Rx paths. Figure 4–21. Rx Path Delay to AUX Output and to AxC Interfaces Receiver (1a) rx_datain Receiver Rx Elastic Transceiver Physical Layer The Rx path delay to the AUX interface is the sum of the following delays: 1 ...
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... Figure 4–2 on page 4–7, uses the recovered clock as input to the PLL that generates 4–6, you must ensure that the reference clock to the clean-up PLL Chapter 4: Functional Description Delay Measurement “Fixed Arria Stratix IV GX Device 6.5 3.5 Figure 4–4 on page 4– ...
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... Chapter 4: Functional Description Delay Measurement number M of cpri_clkout periods. For example, N may be a multiple the M/N frequency ratio may be slightly greater than 1, such as 64/63 or 128/127. The application layer specifies N to ensure the accuracy your application requires. The accuracy of the Rx buffer delay measurement is N/least_common_multiple(N,M) cpri_clkout periods ...
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... Table 4–8 Data Rate > 614.4 Mbps 5 5 4.5 5 Chapter 4: Functional Description Delay Measurement (Table 6–20 on shows the fixed delays between the Arria Stratix IV GX Device Data Rate Data Rate 614.4 Mbps > 614.4 Mbps ...
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... Chapter 4: Functional Description Delay Measurement Rx Path Delay to AUX Output: Calculation Example This section shows you how to calculate the Rx path delay to the AUX output, based on the example shown in page 4–43. This example walks through the calculation for the case of a CPRI MegaCore function that runs at CPRI data rate 3072 Mbps and targets an Arria II GX device ...
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... The delay from there to the individual AxC interfaces is the time the data spends in the mapN Rx buffer, before being written to the AxC interface data channel. In synchronous buffer mode, this delay is one cycle if the sample rate is a multiple of 3.84 MHz, and two cycles otherwise. Refer to page 4– ...
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... AxC interfaces to output from the MAP interface block is the time the data spends in the mapN Tx buffer. This delay is one cycle if the sample rate is a multiple of 3.84 MHz, and two cycles otherwise. Refer to T14, Toffset, Round-Trip Delay, and Round-Trip Cable Delay Calculations The round-trip cable delay is the delay from the REC end of the CPRI downlink to the REC end of the CPRI uplink ...
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... CPRI RE masters and CPRI RE slaves to determine the round-trip delay. The value in the rx_round_trip_delay field of the CPRI_ROUND_DELAY register is meaningful only in CPRI REC and RE masters. It records the round-trip delay for the current hop only, as shown in To determine the round-trip delay of a full multi-hop system, you must add together the values in the CPRI_ROUND_DELAY registers of the REC and RE masters in the system, plus the delays through the external routers ...
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... Chapter 4: Functional Description Data Link Layer for Fast Control and Management Channel (Ethernet) Data Link Layer for Fast Control and Management Channel (Ethernet) In the CPRI MegaCore function, the Ethernet Media Access Control (MAC), or fast data link layer, passes Ethernet data from the CPU interface to the CPRI transmitter interface block, and from the CPRI receiver block to the CPU interface ...
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... Broadcast filtering: Accept all packets with destination MAC address 0xFFFFFFFFFFFF, the Ethernet broadcast address. To enable broadcast filtering, set the broadcast_en bit of the ETH_CONFIG_1 register. CPRI MegaCore Function User Guide Chapter 4: Functional Description Data Link Layer for Fast Control and Management Channel (Ethernet) December 2010 Altera Corporation Chapter 6, ...
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... Chapter 4: Functional Description Data Link Layer for Slow Control and Management Channel (HDLC) Ethernet Rx Buffer Status The CPRI MegaCore function reports relevant Ethernet Rx buffer status to the CPU interface by updating the following fields of the ETH_RX_STATUS register: ■ The ETH_RX_STATUS rx_ready bit indicates that at least one word of data is available in the Ethernet Rx buffer and ready to be read. ■ ...
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... Ethernet MAC block. After the cpri_mii_txrd signal is asserted, the external Ethernet block asserts the cpri_mii_txen signal to indicate it is CPRI MegaCore Function User Guide Chapter 4: Functional Description MII Interface to an External Ethernet Block HDLC Bit Rate Minimum CPRI Line Rate ...
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... The MII interface transmitter module deasserts the cpri_mii_txrd signal in the cycle following each cycle in which it receives data. It may remain deasserted for multiple cycles, to prevent buffer overflow. While the cpri_mii_txrd signal remains low, the external Ethernet block must maintain the data value on cpri_mii_txd ...
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... Ethernet block txen asserted 2 cycles in which txrd is asserted Ethernet packet Chapter 4: Functional Description MII Interface to an External Ethernet Block No txen response to 2 cycles in which txrd asserted Idle Figure 4–23 shows No txen response ...
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... Chapter 4: Functional Description MII Interface to an External Ethernet Block If cpri_mii_txen is deasserted while cpri_mii_txrd is deasserted, and is not reasserted in the cycle following the reassertion of cpri_mii_txrd, then the CPRI MII Interface transmitter inserts a T symbol in the packet; therefore, the external Ethernet block must reassert cpri_mii_txen in the cycle following reassertion of cpri_mii_txrd, during transmission of an Ethernet packet on cpri_mii_txd ...
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... For more information about the MII interface receiver module, refer to Interface Receiver Signals” on page CPRI MegaCore Function User Guide 5–6. Chapter 4: Functional Description MII Interface to an External Ethernet Block “CPRI MII December 2010 Altera Corporation ...
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... December 2010 Altera Corporation Table 5–6 list the input and output signals of the Physical layer of Figure 4–9 on page 4–17 Description Description for a circuit that shows how to enforce synchronous deassertion Description 5. Signals for details of the I/O CPRI MegaCore Function User Guide ...
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... CPRI MegaCore functions Description Table 6–21 on page 6–10. Description Resets the PLL. Signal must be asserted after PLL reconfiguration. Connect to the areset signal for the PLL. When this signal is asserted, the PLL counters are updated with the contents of the scan chain ...
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... Chapter 5: Signals Physical Layer Signals Transceiver Signals Table 5–6 lists the transceiver signals that are connected directly to the transceiver block. In many cases these signals must be shared by multiple transceiver blocks that are implemented in the same device Table 5–6. Transceiver Signals (Part Signal Direction ...
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... Use the gxb_rx_disperr signal to determine whether this signal indicates a code group violation or a disparity error. For details, refer to the relevant device handbook. for information about how to successfully combine multiple high-speed Chapter 5: Signals Physical Layer Signals December 2010 Altera Corporation ...
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... December 2010 Altera Corporation for details about the Avalon-MM interface. Description CPU clock signal. CPU peripheral reset. This reset is associated with the cpu_clk clock. cpu_reset can be asserted asynchronously, but must stay asserted at least one cpu_clk cycle and must be de-asserted synchronously with cpu_clk. Refer to Figure 4– ...
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... Ethernet block. All bits are deasserted during reset, and all bits are asserted after reset until the CPRI MegaCore function achieves frame synchronization. Description Clocks the MII transmitter interface. The cpri_clkout clock drives this signal. Valid signal from the external Ethernet block, indicating the presence of valid data on cpri_mii_txd[3:0] ...
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... Data is valid one mapN_rx_clk clock cycle after the Output read-ready bit is asserted. Bits [15:0] are the I component of the IQ sample. Bits [31:16] are the Q component of the IQ sample. 5–7 Description for a circuit that shows how to enforce CPRI MegaCore Function User Guide ...
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... CPRI MegaCore Function User Guide Direction Description Valid signal for each antenna-carrier interface in FIFO mode. This signal is asserted when the MAP_N Rx buffer exceeds the threshold level in the map_rx_ready_thr field of the CPRI_MAP_RX_READY_THR register. Although each data channel ...
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... Resynchronization signal for use in synchronous buffer mode. When the map_tx_sync_mode bit in the CPRI_MAP_CONFIG register is set to Input 1, the MAP transmitter interface is in synchronous buffer mode. This signal is synchronous to the Description Figure 4–8 on page 4–14 mapN_tx_clk clock. CPRI MegaCore Function User Guide 5–9 ...
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... AxC interfaces and to map interface clock gating to save power. Table 5–13 list the signals on the CPRI MegaCore function Table 5–12 Chapter 5: Signals Auxiliary Interface Signals Description 6–18). (Table 6–47 on through Table 5–13 are clocked by the December 2010 Altera Corporation ...
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... December 2010 Altera Corporation Bit Description cpri_rx_rfp: Synchronization pulse for start radio frame. The pulse occurs at the start of the radio frame on the CPRI receiver interface. cpri_rx_start: Indicates the start of the first basic frame on the AUX interface, and can be used by an AxC software application to trigger the AxC-specific resynchronization signal used in MAP synchronous buffer mode ...
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... Table 6–38 on page for the duration of the basic frame. cpri_tx_rfp: Synchronization pulse for start radio frame. [0] The pulse occurs at the start of the radio frame on the CPRI transmitter interface. Chapter 5: Signals Auxiliary Interface Signals Description 6–16. The signal is asserted December 2010 Altera Corporation ...
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... K28.5 character insertion in the outgoing CPRI frame, which occurs when Z=X=0. If you do not deassert the mask bits during K28.5 character insertion in the outgoing CPRI frame, the cpri_tx_error output signal is asserted in the following cpri_clkout cycle. 5–13 Description CPRI MegaCore Function User Guide ...
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... Signal Direction extended_rx_status_data Output [11:0] CPRI MegaCore Function User Guide Bits Description cpri_rx_los: CPRI receiver LOS indication (active high). This [11] bit reflects the value in the rx_los field of the CPRI_INTR register (Table 6–4 on page 6–2). cpri_rx_lcv: Current CPRI receiver 8B/10B line code violation [10:8] count in current clock cycle ...
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... Output hw_reset_req Input hw_reset_assert December 2010 Altera Corporation Description Extended delay measurement clock. Reset for extended delay measurement block.This reset is associated with the clk_ex_delay clock. reset_ex_delay can be asserted asynchronously, but must stay asserted at least one clock cycle and must be de-asserted synchronously with the clock with which it is associated. Refer to Figure 4– ...
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... CPRI MegaCore Function User Guide Chapter 5: Signals Clock and Reset Interface Signals December 2010 Altera Corporation ...
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... Table 6–2. CPRI MegaCore Function Register Address Ranges Address Range 0x00–0x4C 0x50–0xF0 0xF4–0x1FC 0x200–0x24C 0x250–0x2FC 0x300–0x334 December 2010 Altera Corporation Description Read to clear Read-only Read/write Unused bits/read as 0 Write-only; read as 0 Interface CPRI Interface Registers MAP Interface and AUX Interface Configuration Registers ...
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... Hardware Reset From Control Word Physical Layer Loopback Control CPRI Control and Management Configuration CPRI Control and Management Status Receiver Delay Control Receiver Delay Round Trip Delay Extended Delay Measurement Configuration Extended Delay Measurement Status Auto-Rate Negotiation Pending Interrupt Status Access ...
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... Access [31:6] UR0 RSRV [5] RW tx_enable December 2010 Altera Corporation Function Reserved. Radio frame pulse received. This bit is asserted every 10 ms. CPRI receive clock is not synchronous with system clock (cpri_clkout). This alarm is asserted each time mismatches are found between the recovered CPRI receive clock and the system clock (1) cpri_clkout ...
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... Most recent received CPRI control word from CPRI hyperframe position Z.x.0, where x is the index in the cpri_ctrl_index field of the CPRI_CTRL_INDEX register. Chapter 6: Software Interface CPRI Interface Registers Default 3'h0 1'h0 1'h0 Default 24'h0 8'h0 Default 24'h0 8'h0 December 2010 Altera Corporation ...
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... RSRV [7] reset_gen_done_hold [6] reset_gen_done [5] reset_detect_hold [4] reset_detect December 2010 Altera Corporation Function Reserved. Control byte transmit enable. CPRI control byte to be transmitted in CPRI hyperframe position Z.x.0, where x is the index in the cpri_ctrl_index field of the CPRI_CTRL_INDEX register. Function Reserved. Number of line code violations (LCVs) detected in the 8B/10B decoding block in the transceiver. Enables CPRI link debugging. This register saturates at the value 255 ...
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... Indicates that reset resynchronization is detected. This bit is typically set when the CPRI receiver clock and cpri_clkout (1) have different frequencies, as measured in the physical layer internal loopback path. Reserved. Chapter 6: Software Interface CPRI Interface Registers Default 1'h0 1'h0 1'h0 1'h0 “MegaCore Default 27'h0 1’h0 2'h0 December 2010 Altera Corporation ...
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... Table 6–15. CPRI_CM_STATUS—CPRI Control and Management Status—Offset: 0x2C (Part Field Bits [31:12] UR0 RSRV [11] rx_slow_cm_rate_valid December 2010 Altera Corporation Function Physical layer loopback mode. The following values are defined loopback. 1: Full CPRI frame loop. Incoming CPRI data and control words are sent back as-is in outgoing CPRI communication ...
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... Initial buffer delay with which to align the Rx elastic buffer. After you modify the (1) RW value of this field, you must set the rx_buf_resync bit to resynchronize the buffer. Chapter 6: Software Interface CPRI Interface Registers Default 3’h0 4–51. 1'h0 1'h0 6’h0 Default 15'h0 1’h0 0 WIDTH_RX_BUF-1 2 December 2010 Altera Corporation ...
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... RO Maximum value Current byte-alignment delay. Access Function Reserved. Measured round trip delay from cpri_tx_rfp to RO cpri_rx_rfp. Unit is cpri_clkout clock periods. Function Reserved. Integration period for extended delay measurement. Program this field with the user-defined value N, where M/N = clk_ex_delay period / cpri_clkout period. Refer to Receive Buffer Delay Calculation Example” ...
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... Access Function UR0 Reserved. Indicates an los_lcv interrupt is pending (the interrupt RW occurred but is not yet serviced). UR0 Reserved. Chapter 6: Software Interface CPRI Interface Registers Default 28’h0 As specified in CPRI parameter Figure B–2 for an editor 4’h0 Default 26’h0 1’h0 4’h0 December 2010 Altera Corporation ...
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... Table 6–25. CPRI_TX_PROT_VER— Tx Protocol Version —Offset: 0x58 Field Bits [31:8] RSRV [7:0] tx_prot_version December 2010 Altera Corporation Access Function Indicates a hw_reset interrupt is pending (the interrupt occurred but is not yet serviced slave, this bit is set when a reset request is detected in incoming CPRI communication at Z.130.0, but neither the ...
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... Received scrambler seed. The receiver descrambles the RO incoming CPRI communication based on this seed. Chapter 6: Software Interface CPRI Interface Registers Default 1’h0 31’h0 Default 1’h0 31’h0 December 2010 Altera Corporation ...
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... RW map_15bit_mode [3] RW map_tx_sync_mode [2] RW map_rx_sync_mode December 2010 Altera Corporation Name CPRI Mapping Features Configuration Basic UMTS/LTE Mapping Configuration K Parameter Config for Advanced Table-Based Mapping Advanced Mapping Configuration Table Index Advanced Mapping Rx Configuration Table Advanced Mapping Tx Configuration Table MAP Rx Frame Offset ...
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... Rx and Tx tables. The value in this RW field determines the table entries that appear in the CPRI_MAP_TBL_RX and CPRI_MAP_TBL_TX registers. Chapter 6: Software Interface Default 2’h0 (Note 1) Default 19’h0 5’h0 3’h0 5’h0 Default 0 0 (Note 1) Default 21’h0 11’h0 December 2010 Altera Corporation ...
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... RW map_rx_offset_x Table 6–36. CPRI_MAP_OFFSET_TX—MAP Tx Frame Offset—Offset: 0x11C (Part Field Bits Access [31:17] UR0 RSRV [16] RW map_tx_hf_resync December 2010 Altera Corporation Access Function UR0 Reserved. RW Starting bit position of IQ sample in timeslot. UR0 Reserved. RW AxC interface number. UR0 Reserved. ...
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... CPRI frame buffer to be prepared for transmission on the CPRI link. Basic frame number for start of read of CPRI MAP transmitter AxC container block from each enabled mapN Tx buffer. The CPRI IP core reads the data from the mapN Tx buffer and routes it to the CPRI frame buffer to be prepared for transmission on the CPRI link ...
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... If this CPRI MegaCore function has more than 16 antenna-carrier interfaces (N_MAP > 16), the status for antenna-carrier interfaces 0 through the register at offset 0x140, and the status for antenna-carrier interfaces 16 and the register at offset 0x144. The maximum number of antenna-carrier interfaces in the CPRI MegaCore function is 24. December 2010 Altera Corporation Function Reserved. ...
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... Indicates MAP Tx buffer underflow in the corresponding antenna-carrier interfaces. Indicates MAP Tx buffer overflow in the RC corresponding antenna-carrier interfaces. Chapter 6: Software Interface Default 0 (N_MAP)’h7F (all 1s) Default 0 (N_MAP)’h7F (all 1s) (Note 1) Function Default 16'h0 16'h0 (Note 1) Function Default 16'h0 16'h0 December 2010 Altera Corporation ...
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... RO rx_length [2] RO rx_abort [1] RO rx_eop [0] RO rx_ready December 2010 Altera Corporation Table 6–48 Table 6–49 through Table 6–64 describe the Ethernet registers in the Name Ethernet Receiver Module Status Ethernet Transmitter Module Status Ethernet Feature Configuration 1 Ethernet Feature Configuration 2 Ethernet Rx Control ...
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... RO Reserved. Chapter 6: Software Interface Ethernet Registers Default 29'h0 1’h0 1’h0 1’h0 Default 11'h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 2’h0 1’h0 1'h0 December 2010 Altera Corporation ...
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... RSRV [3:2] WO tx_length [1] WO tx_discard [0] WO tx_eop December 2010 Altera Corporation Function Reserved. Enables insertion of Ethernet frame check sequence (FCS) at the end of the Ethernet frame. Function Reserved. Indicates that the Ethernet receiver module should discard the current Ethernet Rx frame. Function Ethernet Rx frame data. If the Ethernet receiver module takes Ethernet data from this register, if data is not ready when the module expects it, the Ethernet receiver module aborts the packet ...
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... Transmit store-and-forward mode. In store-and-forward mode, a full packet is stored in the Tx buffer before transmission starts. Packets longer than the Tx buffer are aborted. Chapter 6: Software Interface Ethernet Registers Default 1'h0 Default 1'h0 Default 16'h0 16'h0 Default 32'h0 Default 32'h0 Default 15’h0 16’h0004 1'h0 December 2010 Altera Corporation ...
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... Table 6–66. HDLC_RX_STATUS—HDLC Receiver Module Status—Offset: 0x300 (Part Field Bits Access [31:7] UR0 RSRV [6] RO rx_ready_block [5] RO rx_ready_end December 2010 Altera Corporation Access Function RO Number of frames received from the CPRI receiver. Access Function RO Number of frame transmitted to the CPRI transmitter. Table 6–65 provides a memory map for the Table 6–66 through Table 6– ...
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... HDLC Tx interrupt enable. RW HDLC Rx interrupt enable. RW HDLC global interrupt enable. Chapter 6: Software Interface HDLC Registers Default 2’h0 1’h0 1’h0 1’h0 Default 29'h0 1’h0 1’h0 1’h0 Default 11'h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 December 2010 Altera Corporation ...
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... RO rx_data Table 6–72. HDLC_RX_DATA_WAIT—HDLC Rx Data with Wait-State Insertion—Offset: 0x318 Field Bits Access [31:0] RO rx_data December 2010 Altera Corporation Access Function Enable reception of Rx HDLC frames longer than 1536 RW bytes. UR0 Reserved. Indicates that a length check is performed on Rx packets, RW and those with length less than 64 bytes are discarded ...
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... Transmit store-and-forward mode. In store-and-forward mode, a full packet is stored before transmission starts. Packets longer than the Tx buffer are aborted. Chapter 6: Software Interface HDLC Registers Default 28'h0 1’h0 1'h0 1’h0 Default 1'h0 Default 1'h0 Default 25'h0 6'h0 Default 15’h0 16’h0004 1'h0 December 2010 Altera Corporation ...
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... Table 6–78. HDLC_CNT_RX_FRAME—HDLC Receiver Module Frame Counter—Offset: 0x330 Field Bits [31:0] hdlc_cnt_rx_frame Table 6–79. HDLC_CNT_TX_FRAME—HDLC Transmitter Module Frame Counter—Offset: 0x334 Field Bits [31:0] hdlc_cnt_tx_frame December 2010 Altera Corporation Access Function RO Number of frames received from the CPRI receiver. Access Function RO Number of frame transmitted to the CPRI transmitter. 6–27 ...
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... CPRI MegaCore Function User Guide Chapter 6: Software Interface HDLC Registers December 2010 Altera Corporation ...
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... MegaCore function’s interfaces. The initialization process requires that the testbench module write to and read from the CPRI MegaCore function registers through its CPU interface. December 2010 Altera Corporation Transmission and Reception of Data on Interface Antenna-Carrier ...
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... Cyclone IV GX device. Figure 7–1. CPRI MegaCore Function Non-MII Interface Demonstration Testbench (tb_altera_cpri.vhd) tb_altera_cpri Altera Testbench Figure 7–2. CPRI MegaCore Function MII Interface Demonstration Testbench (tb_altera_cpri_mii.vhd) tb_altera_cpri_mii Altera Testbench CPRI MegaCore Function User Guide illustrate the auto-rate negotiation testbenches, ...
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... Chapter 7: Testbenches Introduction Figure 7–3. CPRI MegaCore Function MII Interface No IQ Demonstration Testbench (tb_altera_cpri_mii_noiq.vhd) tb_altera_cpri_mii_noiq Altera Testbench Figure 7–4. CPRI MegaCore Function Auto-rate Negotiation Demonstration Testbench (tb_altera_cpri_autorate.vhd) tb_altera_cpri_autorate Altera Testbench December 2010 Altera Corporation Reference Clock MII Interface gxb_txdataout gxb_rxdatain aux_tx_status_data, ...
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... AUX interface after loopback through the CPRI link. ■ Generates a sequence of 32-bit words and sends the data sequence to each antenna-carrier interface that is enabled. The tb_altera_cpri and tb_altera_cpri_mii testbenches support three antenna-carrier interfaces; the tb_altera_cpri_autorate, tb_altera_cpri_c4gx_autorate, and tb_altera_cpri_mii_noiq testbenches support no antenna-carrier interfaces. ...
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... When these values appear in the waveform display, the CPRI link is up and ready to receive and send data. Next, basic programming of the internal registers is performed in the DUT to allow CPRI communication. tb_altera_cpri and tb_altera_cpri_mii DUTs. For a full description of each register, refer to Chapter 6, Software Table 7–3. Testbench Registers ...
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... If you use a different path or file name, you must edit the compile_<variation>.do file to refer to the correct file for the DUT. (2) Altera does not support an example testbench for an RE slave DUT slave in loopback configuration cannot achieve frame synchronization, because the receive CPRI interface must lock onto the K28.5 character before the transmit CPRI interface can begin sending K28 ...
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... Chapter 7: Testbenches Running the Testbenches 3. If you are running the tb_altera_cpri_autorate or tb_altera_cpri_c4gx_autorate testbench, you must generate the appropriate Memory Initialization Files (.mif) to configure the altgx_reconfig block. If you are running the tb_altera_cpri_c4gx_autorate testbench, the following steps also generate the appropriate Memory Initialization Files (.mif) to configure the altpll_reconfig block ...
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... In the ModelSim simulator, change directories to your testbench directory, <working directory>/cpri_top_level_testbench/altera_cpri. This folder contains the testbench VHDL (.vhd) files and the .do files to run the testbenches set up the library files for the Mentor Graphics ModelSim SE simulator, perform the following steps: a. Create a library folder, < ...
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... To prepare to simulate VHDL files with ModelSim SE, perform the following ■ edits: Change all instances of src/cpri_top_level.vho to ■ ../../cpri_top_level_sim/cpri_top_level.vho. Change all instances of test/tb_altera_cpri[_<variation>].vhd to ■ tb_altera_cpri[_<variation>].vhd. For the auto-rate negotiation testbenches, change all remaining instances of ■ src/<file>.vhd to <file>.vhd. To prepare to simulate Verilog HDL files with ModelSim SE, perform the ■ ...
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... CPRI MegaCore Function User Guide Chapter 7: Testbenches Running the Testbenches December 2010 Altera Corporation ...
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... This appendix describes the most basic initialization sequence for a CPRI MegaCore function. To initialize the CPRI MegaCore function, follow these steps configure the Altera FPGA with your design, download your .sof file to the FPGA. 2. Perform the following two actions simultaneously: Perform a global CPRI MegaCore function reset by asserting the following ■ ...
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... A–2 CPRI MegaCore Function User Guide Appendix A: Initialization Sequence December 2010 Altera Corporation ...
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... For information about the Cyclone IV GX transceiver blocks and MPLLs, refer to the Transceivers section of the Cyclone IV Device Handbook. For information about the ALTPLL_RECONFIG megafunction, refer to the (ALTPLL_RECONFIG) Megafunction User December 2010 Altera Corporation B. Implementing CPRI Link Auto-Rate Phase-Locked Loops Reconfiguration Guide. Negotiation ...
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... MHz gxb_refclk 76.8 MHz 122.88 MHz 153.6 MHz Cleanup PLL (2) gxb_pll_inclk ALTGX_RECONFIG ALTPLL_RECONFIG (for Cyclone IV GX devices) Design Implementation datarate_en AUTORATE_CONFIG datarate_set Register CPRI MegaCore Function ALTGX rx_cruclk pll_clkout pll_inclk reconfig_fromgxb reconfig_togxb To MPLL in Cyclone IV GX devices December 2010 Altera Corporation ...
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... CPRI MegaCore function, your hardware and software must perform the following steps: 1. Confirm that the i_datarate_en bit of the AUTO_RATE_CONFIG register is set to 1. The AUTO_RATE_CONFIG register is described in read this value on the datarate_en output signal. December 2010 Altera Corporation AUTORATE_CONFIG (1) 15.36 MHz 30.72 MHz 61 ...
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... CPRI_CONFIG register. The value 0x3 on the extended_rx_status_data[1:0] signal confirms that the CPRI receiver has achieved frame synchronization. CPRI MegaCore Function User Guide Appendix B: Implementing CPRI Link Auto-Rate Negotiation Running Auto-Rate Negotiation Figure 4–10 on page 4–20 December 2010 Altera Corporation attempts ...
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... Added GUI parameter to enable auto-rate negotiation and two signals to support ■ visibility of the feature status. July 2010 10.0 Enhanced descriptions of MII interface, MAP interface synchronous buffer mode, and ■ use of AUX interface mask. Enhanced testbench suite to include two new testbenches, to demonstrate operation ■ ...
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... GUI. Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file. Indicate document titles. For example, Stratix IV Design Guidelines. Indicates variables. For example ...