IP-CPRI Altera, IP-CPRI Datasheet - Page 46

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–22
CPU Interface Module
CPRI MAP Interface Module
CPRI MegaCore Function User Guide
1
Altera recommends that you assert the config_reset signal to clear all control
transmit table entries at startup before you set the tx_ctrl_insert_en bit in the
CPRI_CONTROL register.
When no data is available to transmit on the CPRI interface, the transmitter transmits
the standard frame sequence with zeroed control words and all-zero data.
When the tx_prot_version field of the CPRI_TX_PROT_VER register
page
according to the CPRI V4.1 Specification, using the seed in the tx_scr_seed field of
the CPRI_TX_SCR_SEED register
The transceiver is an embedded ALTGX megafunction in the Arria II GX, Arria II GZ,
Cyclone IV GX, or Stratix IV GX device. The transceiver transmitter implements
8B/10B encoding and the deterministic latency protocol. It transforms the 16-bit
parallel input data to the Arria II GX or Cyclone IV GX transmitter, or 32-bit parallel
input data to the Arria II GZ or Stratix IV GX transmitter, to 8-bit data before 8B/10B
encoding. The 10-bit encoded data is then serialized and sent to the CPRI link
differential output pins.
The deterministic latency protocol is designed to meet the 16.276 ns round-trip delay
measurement accuracy requirements R21 and R21A of the CPRI specification.
The CPU interface module provides an Avalon-MM slave interface that accesses all
registers in the CPRI MegaCore function. This module can communicate with an
on-chip or external processor, an Ethernet channel, and an HDLC channel.
The input to the CPU interface port from the processor is synchronized with the
cpu_clk clock.
Each of the three sources of input to the CPU interface communicates with the CPRI
MegaCore function by reading and writing registers through a single Avalon-MM
port on the CPU interface. Arbitration among the different sources must occur outside
the CPRI MegaCore function.
For more information about the CPRI MegaCore function registers, refer to
Software
The CPRI MegaCore function communicates with the RF implementations
(antenna-carriers) through multiple AxC interfaces, or data channels. A CPRI
MegaCore function configured with a MAP interface module can have as many as 24
data channels, and as few as one data channel. If a CPRI MegaCore function is
configured with zero data channels, it does not have a MAP interface module. The
Number of antenna/carrier interfaces value you set in the parameter editor
determines the number of channels in your MegaCore function configuration. Each
data channel communicates with the corresponding RF implementation using two
32-bit Avalon-ST interfaces, one incoming and one outgoing.
The CPRI MAP interface module controls transmission and reception of data on the
AxC interfaces.
6–11) holds the value 2, the low-level CPRI transmitter scrambles the data words
Interface.
(Table 6–26 on page
6–12).
December 2010 Altera Corporation
Chapter 4: Functional Description
(Table 6–25 on
CPU Interface Module
Chapter 6,