IP-CPRI Altera, IP-CPRI Datasheet
IP-CPRI
Specifications of IP-CPRI
Related parts for IP-CPRI
IP-CPRI Summary of contents
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... CPRI MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01062-4.0 CPRI MegaCore Function Document last updated for Altera Complete Design Suite version: Document publication date: User Guide 11.0 May 2011 Subscribe ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... CPRI IP Core Basic Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 High-Speed Transceiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 MII Interface Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 MAP Interface Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6 Clock Diagrams for the CPRI IP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6 CPRI Communication Link Line Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12 CPRI IP Core Reset Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14 ...
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... Tx Transceiver Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–46 T14, Toffset, Round-Trip Delay, and Round-Trip Cable Delay Calculations . . . . . . . . . . . . . . . . . . 4–46 Round-Trip and Cable Delay Calculations for a Single-Hop Configuration . . . . . . . . . . . . . . . . 4–47 Round-Trip Calculations for a Multihop Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53 Data Link Layer for Fast Control and Management Channel (Ethernet 4–54 Ethernet Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–55 Ethernet Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4– ...
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... Running the Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6 Appendix A. Initialization Sequence Appendix B. Implementing CPRI Link Autorate Negotiation Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1 Configuring the CPRI IP Core for Autorate Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3 Running Autorate Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3 Appendix C. Porting a CPRI IP Core from the Previous Version of the Software Additional Information Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info– ...
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... CPRI MegaCore Function User Guide Contents May 2011 Altera Corporation ...
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... The Altera CPRI MegaCore Interface (CPRI) specification. CPRI is a high-speed serial interface designed for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE). The CPRI IP core targets high-performance, remote, radio network applications. You can configure the CPRI IP core REC. ...
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... You can configure your CPRI IP core with zero, one, or multiple antenna-carrier interfaces. (2) You can configure your CPRI IP core with an Ethernet MAC block or an MII block. The two options are mutually exclusive. CPRI IP Core Features The CPRI IP core has the following features: Complies with ■ ...
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... Vendor-specific subchannel (VSS) communication on the CPRI link. ■ Diagnostic parallel reverse loopback paths. ■ ■ Includes the following additional interfaces: Interface to external or on-chip processor, using the Altera Avalon ■ Memory-Mapped (Avalon-MM) interconnect specification for bus widths bits. Ethernet communication interfaces that support Ethernet and HDLC ■ ...
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... The IP core meets all functional and timing requirements for the device family and can be used in production designs. Table 1–2 lists the level of support offered by the CPRI IP core for each Altera device family. Table 1–2. Device Family Support ® ...
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... Arria II GX (EP2AGX260FF35C4 for line rates 614.4, 1228.8, 2457.6, and ■ 3072 Mbps; EP2AGX125EF45I3 for line rates 4915.2 and 6144 Mbps) Arria II GZ (EP2AGZ225FF35C3) ■ ■ Stratix IV (EP4SGX360NF45C2) Table 1–3. CPRI IP Core FPGA Resource Utilization (Part Parameters Device Line Rate Include MAC (Mbps) Block Yes 614 ...
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... Table 1–3. CPRI IP Core FPGA Resource Utilization (Part Parameters Device Line Rate Include MAC (Mbps) Block Yes 1228.8, 2457.6, Arria II GZ 3072, (continued) 4915.2, 6144 No Yes 614.4 No Stratix IV GX Yes 1228.8, 2457.6, 3072, 4915.2, 6144 No CPRI MegaCore Function User Guide ...
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... Chapter 1: About This MegaCore Function Performance and Resource Utilization Table 1–4 shows results obtained with the Quartus II software v11.0 for the following device: Cyclone IV GX (EP4CGX150DF31C7) ■ Table 1–4. CPRI IP Core Cyclone IV GX Resource Utilization Device Line Rate (Mbps) 614.4 Cyclone IV GX 1228.8, 2457 ...
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... CPRI Line Rate (Mbps) 1228.8 2457.6 3072.0 –4 –4 –4 Item MegaCore IP Library Release Notes and Chapter 1: About This MegaCore Function Release Information 4915.2 6144 –4 –3 Description 11.0 May 2011 IP-CPRI 00CB 6AF7 Errata. Altera does not verify May 2011 Altera Corporation ...
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... CPRI IP core only when you are satisfied with its functionality and performance, and you want to take your design to production. After you purchase a license for the CPRI IP core, you can request a license file from the Altera website at When you request a license file, Altera emails you a license.dat file. If you do not have internet access, contact your local Altera representative ...
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... Your design stops working after the hardware evaluation time expires. The CPRI IP core then behaves as if the reset and cpu_reset signals are asserted: the CPRI link and the CPU interface reset. The transceivers do not reset, because the transceiver quad might be shared with other designs, IP cores, and megafunctions. ...
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... You can customize the CPRI IP core to support a wide variety of applications. You use the MegaWizard Plug-In Manager in the Quartus II software to parameterize a custom IP core variation in a CPRI parameter editor. The CPRI parameter editor lets you interactively set parameter values and select optional ports. ...
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... If you generate the CPRI IP core instance in a Quartus II project, you are prompted to add the Quartus II IP File (.qip) to the current Quartus II project. You can also turn on Automatically add Quartus II IP Files to all projects. The .qip file is generated by the parameter editor, and contains information about the generated IP core ...
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... For information about the Quartus II software and the MegaWizard Plug-In Manager, refer to the Quartus II Help topics “About the Quartus II Software” and “About the MegaWizard Plug-In Manager”. For a complete list of models or libraries required to simulate the CPRI IP core, refer to the compile[_<variation>]_<HDL>.do scripts provided with the demonstration testbenches described in ...
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... You must ensure that a single calibration clock source drives the gxb_cal_blk_clk input to each CPRI IP core (or any other megafunction or user logic that uses the ALTGX megafunction). When you merge multiple CPRI IP cores in a single transceiver block, the same signal must drive gxb_powerdown to each of the CPRI IP core variations and other megafunctions, Altera IP cores, and user logic that use the ALTGX megafunction ...
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... You customize the CPRI IP core by specifying parameters in the CPRI parameter editor, which you access from the MegaWizard Plug-In Manager in the Quartus II software. This chapter describes the parameters and how they affect the behavior of the CPRI IP core. You can modify parameter values to specify the following CPRI IP core properties: ■ ...
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... By default, this parameter is turned off. Transceiver Starting Channel Number You can specify the starting number for the CPRI IP core transceiver. For a CPRI IP core master, the Master transceiver starting channel number specifies the starting channel number for the transceiver. ...
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... The combination of CPRI IP core line rate, sampling width, and sampling rate restricts the number of active antenna-carrier interfaces your CPRI IP core can support. For example, if your CPRI IP core operates at line rate 3.072 Gbps, it can support as many as 20 active antenna-carrier interfaces, but if your CPRI IP core operates at line rate 1 ...
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... The value you specify for Number of antenna/carrier interfaces is referred to as N_MAP in this user guide. For more information about the antenna-carrier interfaces in a CPRI IP core, refer to “CPRI MAP Interface Module” on page CPRI MegaCore Function User Guide ...
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... The CPRI specification divides the protocol into a physical layer (layer 1) and a data link layer (layer 2). Layer 1 is implemented in the CPRI interface module. This chapter describes the individual interfaces of the CPRI IP core and how data passes between them. This chapter contains the following sections: ■ ...
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... You can configure your CPRI IP core with zero, one, or multiple IQ data channels. (2) You can configure your CPRI IP core with an Ethernet MAC block or an MII block. The two options are mutually exclusive. The following sections describe the individual interfaces and clocks. ...
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... For information about the Avalon-MM interface, refer to MAP Interface The CPRI MAP interface comprises the individual antenna-carrier interfaces, or data channels, through which the CPRI IP core transfers IQ sample data to and from the RF implementation. The CPRI MAP interface is implemented as an incoming and an outgoing Avalon-ST interface. ...
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... The CPRI IP core has a variable number of clock domains, depending on the number of antenna-carrier interfaces. In addition to the high-speed clock domains inside the Arria II GX, Arria II GZ, Cyclone IV GX, or Stratix IV GX transceiver, the CPRI IP core contains three basic clock domains, two clock domains for the MII interface implemented, and two clock domains for each antenna-carrier interface ...
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... PLL in a CPRI IP core configured in ■ slave clocking mode. If the CPRI IP core is configured in master clocking mode, it does not use this clock. In master clocking mode, you must tie this input slave clocking mode, the gxb_pll_inclk clock connects to the pll_inclk input signal of the Arria II GX, Arria II GZ, or Stratix IV GX transceiver’ ...
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... REC masters in all four device families with CPRI line rate 0.6144 Gbps. CPRI MegaCore Function User Guide 4–26. Figure 4–5 show the clocking schemes for CPRI IP cores configured as show the clock diagrams for CPRI IP cores configured as RE slaves, RE Chapter 4: Functional Description Clocking and Reset Structure Table 4–4 and Figure 4– ...
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... Clocking and Reset Structure Figure 4–2 shows the clock diagram for a CPRI IP core configured slave with CPRI line rate greater than 0.6144 Gbps in an Arria Cyclone IV GX device. Figure 4–2. CPRI IP Core Slave Clocking in Arria II GX and Cyclone IV GX Devices gxb_refclk rx_cruclk pll_inclk ...
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... Figure 4–3 shows the clock diagram for a CPRI IP core configured as an REC master master with CPRI line rate greater than 0.6144 Gbps in an Arria Cyclone IV GX device. Figure 4–3. CPRI IP Core Master Clocking in Arria II GX and Cyclone IV GX Devices gxb_refclk pll_inclk gxb_txdataout ...
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... Clocking and Reset Structure Figure 4–4 shows the clock diagram for a CPRI IP core configured slave with CPRI line rate greater than 0.6144 Gbps in an Arria Stratix IV GX device. Figure 4–4. CPRI IP Core Slave Clocking in Arria II GZ and Stratix IV GX Devices gxb_refclk rx_cruclk gxb_txdataout ...
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... Figure 4–5 shows the clock diagram for a CPRI IP core configured as an REC master master with CPRI line rate greater than 0.6144 Gbps in an Arria Stratix IV GX device. Figure 4–5. CPRI IP Core Master Clocking in Arria II GZ and Stratix IV GX Devices gxb_refclk pll_inclk gxb_txdataout ...
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... Chapter 4: Functional Description Clocking and Reset Structure Figure 4–6 shows the clock diagram for a CPRI IP core configured slave with CPRI line rate 0.6144 Gbps in an Arria II GX, Arria II GZ, Cyclone IV GX, or Stratix IV GX device. Figure 4–6. CPRI IP Core Slave Clocking at CPRI Line Rate 0.6144 Gbps ...
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... CPRI Communication Link Line Rates The CPRI specification specifies line rates of n × 614.4 Mbps for 10. The CPRI IP core implements line rates of n × 614.4 Mbps for n in {1,2,4,5,8,10}. Cyclone IV GX devices support line rates of n × 614.4 Mbps only for n in {1,2,4,5}. ...
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... Note to Table 4–1: (1) The CPRI IP core supports CPRI line rates 4915.2 Mbps and 6144 Mbps in variations that target Arria II GX devices only for speed grade I3 devices. The cpri_clkout frequency depends only on the CPRI line rate. The pll_clkout frequency depends on the CPRI line rate and on the datapath width through the transceiver. The datapath width is determined by device family, as shown in Figure 4– ...
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... For more information about the requirements for reset signals, refer to Signals. Reset Controller The CPRI IP core has a dedicated reset control module to enforce the specific reset requirements of the high-speed transceiver module. This module generates the recommended reset sequence for the transceiver. The reset signal controls the reset control module ...
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... The hw_reset_assert input signal is asserted while the reset_hw_en bit in the CPRI_HW_RESET register is set. The behavior of a CPRI IP core in slave mode that receives a reset request on the CPRI link depends on the same enable fields in its own CPRI_HW_RESET register. For reset acknowledgements, the reset_hw_en bit also takes precedence over the reset_gen_en bit ...
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... To abort a reset request made by asserting the hw_reset_assert input signal, set the reset_hw_en bit of the CPRI_HW_RESET register CPRI IP core in slave mode indicates that it detects a reset request sent in CPRI communication by setting the reset_detect and reset_detect_hold bits of the CPRI_HW_RESET register. ...
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... Chapter 4: Functional Description Physical Layer ■ Transmitter and receiver with the following features: High-speed data serialization and deserialization ■ Clock and data recovery (receiver) ■ 8B/10B encoding and decoding ■ Frame and control word assembly and delineation ■ Error detection ■ ...
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... Because resynchronizing the Rx elastic buffer resets its pointers, you must ensure that the Rx elastic buffer is empty before it is resynchronized. Program the CPRI_RX_DELAY_CTRL register to realign and resynchronize the Rx elastic buffer. The Rx elastic buffer adds variable delay to the Rx path through the CPRI IP core. Refer to “Extended Rx Delay Measurement” on page ...
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... If scrambling is configured in the CPRI link partner (based on the value at Z.2.0 in the incoming CPRI communication), additional actions and conditions apply on the state machine transitions, according to the CPRI V4.1 Specification. The CPRI IP core sets the values in the CPRI_RX_SCR_SEED register according to these conditions. May 2011 Altera Corporation 4– ...
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... A control receive table contains a 1-byte entry for each of the 256 control words in the current hyperframe. The control receive table entries are updated only when the frame synchronization state machine is in the HFNSYNC2 state, in which the CPRI IP core achieves hyperframe synchronization. To read a control byte, write the frame number X to the CPRI_CTRL_INDEX register and then read the last received #Z ...
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... Appendix B, Implementing CPRI Link Autorate Negotiation logic required to implement autorate negotiation in your design. If you configure your CPRI IP core for autorate negotiation, the IP core includes two output status signals and a register to collect the status information, as well as the internal support to change CPRI line rate according to your design’s input to the transceiver dynamic reconfiguration block ...
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... AxC interfaces, or data channels. A CPRI IP core configured with a MAP interface module can have as many as 24 data channels, and as few as one data channel CPRI IP core is configured with zero data channels, it does not have a MAP interface module. The Number of antenna/carrier interfaces value you set in the parameter editor determines the number of channels in your CPRI IP core configuration ...
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... IQ data block of each basic frame. This number must be less than or equal to the N_MAP value you selected for Number of antenna/carrier interfaces in the parameter editor, which is the number of channels configured in the CPRI IP core instance. The map_n_ac field of the CPRI_MAP_CNT_CONFIG register holds the oversampling factor for the data channels. This value is an integer from The sample rate— ...
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... Container 1 1 The CPRI IP core does not support AxC interface reordering. When the value of map_ac is less than N_MAP, the first map_ac AxC interfaces, of the existing N_MAP interfaces, are active. Note that an active AxC interface transmits and receives data on its data channel based on the values of the relevant map_rx_enable bit of the CPRI_IQ_RX_BUF_CONTROL register and the relevant map_tx_enable bit of the CPRI_IQ_TX_BUF_CONTROL register ...
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... Note to Table 4–4: (1) The maximum number of data channels supported by the CPRI IP core is 24. The numbers in the table that are larger than 24 are hypothetical; the CPRI IP core cannot implement them. May 2011 Altera Corporation ...
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... Table 4–5: (1) The maximum number of data channels supported by the CPRI IP core is 24. The numbers in the table that are larger than 24 are hypothetical; the CPRI IP core cannot implement them. In 16-bit mode, the total number of bits in all the AxC containers in a basic frame is 2 × ...
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... CPRI frame. In 15-bit width mode, the two advanced AxC mapping modes act identically. Because the number of bits in the IQ data block of every CPRI frame is a multiple of 30, packed 15-bit I- and Q-samples fill an AxC container—and one or more CPRI frames—with no spare bytes remaining. ...
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... AxC data in the CPRI frame. For example, for a CPRI IP core running at CPRI data rate 1228.8 Gbps, the number of data bits in a CPRI basic frame is 240. (Refer to in the K field of the CPRI_MAP_TBL_CONFIG register) has value two, 480 bits bytes, of data are sent or received on the data channel. In 16-bit mode, when map_mode has value 2’ ...
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... CPRI MAP Receiver Interface The CPRI MAP receiver interface transmits to the data channels data that the CPRI IP core receives from the CPRI link. The CPRI MAP receiver implements an Avalon-ST interface protocol. Refer to the interface communication signals ...
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... In addition to ensuring that application-specific constraints are accommodated, the system can set the CPRI_START_OFFSET_RX register to an offset that lags the desired frame position in the CPRI transmission, in anticipation of the delays from the CPRI Rx interface and through the antenna-carrier interface Rx buffer. For information about these delays, refer to Figure 4– ...
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... In synchronous buffer mode, because programmed offsets control the mapN Rx buffer pointers, the delay can be quantified. In synchronous buffer mode, this delay is one cycle if the sample rate is a multiple of 3.84 MHz, and two cycles otherwise synchronous buffer mode, Altera recommends that you use sample rates that are integer multiples of 3 ...
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... In addition to ensuring that application-specific constraints are accommodated, the system can set the CPRI_START_OFFSET_TX register to an offset that precedes the desired frame position in the CPRI transmission, in anticipation of the delays through the antenna-carrier interface Tx buffer and out to the CPRI Tx frame buffer. For information about these delays, refer to Figure 4– ...
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... In synchronous buffer mode, because programmed offsets control the mapN Tx buffer pointers, the delay can be quantified. In synchronous buffer mode, this delay is one cycle if the sample rate is a multiple of 3.84 MHz, and two cycles otherwise. PRBS Generation and Validation The CPRI IP core supports generation and validation of several predetermined pseudo-random binary sequences (PRBS) for antenna-carrier interface testing ...
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... AUX receiver transmits data received from the incoming CPRI link. AUX Receiver Module The AUX receiver module transmits data that the CPRI IP core received on the CPRI link to the outgoing AUX Avalon-ST interface. In addition, it provides detailed information about the current state in the Rx CPRI frame synchronization state machine ...
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... The AUX receiver transmits data on the AUX interface in fixed 32-bit words. The mapping to 32-bit words depends on the CPRI IP core line rate. how the data received from the CPRI interface module is mapped to the AUX Avalon-ST 32-bit interface. Figure 4–17. AUX Interface Outgoing Data at Different CPRI Line Rates (Part 614 ...
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... Sequence number on AUX interface 1 2 ... (1) #Z.X.1.0 ... (1) #Z.X.1.1 ... (1) #Z.X.2.2 ... (1) #Z.X.2.3 ... Chapter 4: Functional Description Auxiliary Interfaces 7 #Z.X.14.0 #Z.X.14.1 #Z.X.15.0 #Z.X.15.1 15 #Z.X.15.0 #Z.X.15.1 #Z.X.15.2 #Z.X.15 #Z.X.14.2 #Z.X.15.1 #Z.X.14.3 #Z.X.15.2 #Z.X.14.4 #Z.X.15.3 #Z.X.15.0 #Z.X.15 #Z.X.14.0 #Z.X.15.4 #Z.X.14.1 #Z.X.15.5 #Z ...
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... Light blue table cells indicate control word bytes. White table cells indicate data word bytes. AUX Transmitter Module The AUX transmitter module receives data on the incoming AUX Avalon-ST interface and sends it to the CPRI IP core to transmit on the CPRI link. In addition, it outputs CPRI link frame synchronization information, to enable synchronization of the AUX data. ...
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... Rx delay measurement values available in the CPRI_RX_DELAY and CPRI_EX_DELAY_STATUS delay registers, and makes the round-trip delay measurement available in the CPRI_ROUND_DELAY register. In addition, the CPRI IP core allows you to specify settings that control the degree of delay accuracy in the status registers, by programming the CPRI_RX_DELAY_CTRL and CPRI_EX_DELAY_CONFIG registers. ...
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... T_T4 T_R1 cpri_rx_rfp CPRI requirement R-21 addresses the accuracy of the round-trip cable delay, which is the sum of the T12 and T34 delays. The T12 and T34 delays are assumed to have the same duration. May 2011 Altera Corporation or CPRI_IQ_RX_BUF_CONTROL register, and no delay calculation ...
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... T_txv_RX T_txv_TX optical link The following sections describe the delay through the CPRI IP core on the Rx path and on the Tx path to the SAP—the AUX interface—and the deterministic values for transceiver latency and delay through the IP core. They describe the calculation of the round-trip cable delay T14, the Toffset delay, and the round-trip (SAP to SAP) delay in the single-hop and multihop cases ...
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... The link delay is the delay between the arrival of the first bit radio frame on the CPRI Rx interface and the CPRI IP core internal transmission of the radio frame pulse from the CPRI interface Rx module. The link delay includes the following delays: a ...
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... The CPRI IP core uses a dedicated clock, clk_ex_delay, to measure the Rx buffer delay to your desired precision. The ...
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... CPRI Receive buffer. For example, assume your CPRI IP core runs at data rate 3072 Mbps. In this case, Table 4–1 on page 4–12 cpri_clkout cycle is 1/(76.80 MHz). ...
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... This section shows you how to calculate the Rx path delay to the AUX output, based on the example shown in page 4–43. This example walks through the calculation for the case of a CPRI IP core that runs at CPRI data rate 3072 Mbps and targets an Arria II GX device. To calculate the Rx path delay, follow these steps: 1. Consult Table 4– ...
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... Physical Layer In the CPRI IP core the delay from the AUX interface is fixed. This path has no variable delay component, because it does not cross clock domains. The Tx path delay from the AUX interface comprises the following delays: 1. Fixed delay from the AUX interface through the CPRI low-level transmitter to the transceiver ...
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... Table 4–9: (1) In Arria II GZ and Stratix IV GX devices, two additional cpri_clkout cycles of delay are introduced when the CPRI IP core is configured with autorate negotiation enabled. The first number in each column is the delay when the CPRI IP core is configured with autorate negotiation disabled, and the second number listed in the column is the delay when the CPRI IP core is configured with autorate negotiation enabled. ...
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... Chapter 4: Functional Description Delay Measurement Because the CPRI REC master and the CPRI RE slave might be on different devices, the following formulas specify the source CPRI IP core (REC or RE) for the delays in each calculation. Round-Trip and Cable Delay Calculations for a Single-Hop Configuration The rx_round_trip_delay field of the CPRI_ROUND_DELAY register records the delay between the outgoing cpri_tx_rfp signal and the outgoing cpri_rx_rfp signal ...
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... Tx path delay. However, in your own system you may have to perform a separate calculation for this step. 8. Calculate T14 = rx_round_trip_delay – <REC Rx path delay> – <REC Tx path delay> – 43.75 – 9.5 = 31.75 cpri_clkout cycles CPRI MegaCore Function User Guide 4– ...
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... Round-trip cable delay = T14 – Toffset Round-Trip and Cable Delay Calculation Example 2: Two Arria II GX Devices This example shows the calculation for the case of two link partner CPRI IP cores configured with autorate negotiation enabled on Arria II GX devices single-hop configuration, running at CPRI data rate 3.072 Gbps. ...
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... Round-trip cable delay = T14 – Toffset Round-Trip and Cable Delay Calculation Example 3: Two Different Device Families This example shows the calculation for the case of two link partner CPRI IP cores configured with autorate negotiation enabled in a single-hop configuration, running at CPRI data rate 3.072 Gbps. The REC master is configured on a Stratix IV GX device and the RE slave is configured on an Arria II GX device ...
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... T_T4 is 6.25 cpri_clkout cycles, and according to Table 4–10 on page Tx path delay = T_T4 + T_txv_TX = 6.25 + 3.35 = 9.6 8. Calculate T14 = rx_round_trip_delay – <REC Rx path delay> – <REC Tx path delay> – 43.75 – 9.5 = 32.75 cpri_clkout cycles 9. Calculate Toffset = <RE Rx path delay> + <RE Tx path delay> + <loopback delay> ...
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... Round-trip cable delay = T14 – Toffset Round-Trip and Cable Delay Calculation Example 4: Two Different Device Families This example describes the calculation for the case of two link partner CPRI IP cores configured with autorate negotiation enabled in a single-hop configuration, running at CPRI data rate 3.072 Gbps. The REC master is configured on an Arria II GX device and the RE slave is configured on a Stratix IV GX device ...
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... REC or RE master and the RE slave at the current hop. Half of the resulting value is assumed to be the cable delay in each direction at the current hop. The round-trip cable delay is the sum of all the local round-trip cable delays in the multihop path. May 2011 Altera Corporation = 31.75 – ...
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... Data Link Layer for Fast Control and Management Channel (Ethernet) If you turn on the Include MAC block parameter, your CPRI IP core includes an internal Ethernet Media Access Controller (MAC). If you turn off this parameter, an MII-like interface is available for you to connect to your own external Ethernet MAC. ...
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... Chapter 4: Functional Description Data Link Layer for Fast Control and Management Channel (Ethernet) In the CPRI IP core, the Ethernet MAC, or fast data link layer, passes Ethernet data from the CPU interface to the CPRI transmitter interface block, and from the CPRI receiver block to the CPU interface. The CPRI specification dictates that a CPRI hyperframe that contains Ethernet data also contain a pointer to the start of that data in control byte Z ...
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... To disable MAC address checking, set the mac_check bit of the ETH_CONFIG_1 register. If the mac_check bit is set, the Ethernet receiver accepts all received packets. All CPRI IP core MAC address filters assume the MAC destination address is in the first six bytes of the fast C&M data in the CPRI hyperframe. If the MAC destination address is located elsewhere in the fast C& ...
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... If the internal HDLC block is turned off, attempts to access these registers read zeroes and do not write successfully, as for a reserved register address. In the CPRI IP core, the High-Level Data Link Control (HDLC), or slow data link layer, passes HDLC data between the CPU interface and the CPRI receiver and transmitter interfaces to the CPRI link ...
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... HDLC channel control does not support address filtering ■ MII Interface to an External Ethernet Block You can define a CPRI IP core to bypass the internal Ethernet or HDLC module and communicate directly with an external Ethernet block through an MII-like interface, referred to in this document as the MII interface. This interface is not a true MII, ...
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... Ethernet block asserts the cpri_mii_txen signal to indicate it is ready to provide data. The MII interface transmitter module deasserts the cpri_mii_txrd signal in the cycle following each cycle in which it receives data. It may remain deasserted for multiple cycles, to prevent buffer overflow. While the cpri_mii_txrd signal remains low, the external Ethernet block must maintain the data value on cpri_mii_txd ...
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... Ethernet block. The MII interface receiver module transmits the K nibble to indicate start-of-frame on the MII interface. The J nibble of the start-of-frame is consumed by the CPRI IP core, and is not transmitted on the MII interface. The MII interface receiver module transmits the K nibble and then the data to the cpri_mii_rxd output data bus and asserts the cpri_mii_rxdv signal to indicate that the data currently on cpri_mii_rxd is valid ...
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... Chapter 4: Functional Description MII Interface to an External Ethernet Block The cpri_mii_rxer signal indicates whether or not frame synchronization is achieved. While asserted, it indicates to the external Ethernet block that the data currently on cpri_mii_rxd is not valid. Figure 4–25 illustrates the MII interface receiver protocol. Figure 4–25. CPRI MII Interface Receiver Example ...
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... For more information about the MII interface receiver module, refer to Interface Receiver Signals” on page CPRI MegaCore Function User Guide Chapter 4: Functional Description MII Interface to an External Ethernet Block 5–6. May 2011 Altera Corporation “CPRI MII ...
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... CPRI IP core and custom logic. Transceiver reset. This reset is associated with the reconfig_clk clock. A reset controller module propagates this reset to the CPRI IP core cpri_clkout clock domain as well. reset can be asserted asynchronously, but must stay asserted at least one clock cycle and ...
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... Autorate Negotiation Signals Table 5–4 lists the autorate negotiation signals for the CPRI IP core. These output signals enable the autorate negotiation hardware and software outside the CPRI IP core to quickly monitor autorate negotiation status, and are implemented in all device families. In Cyclone IV GX devices, channel reconfiguration is enabled to support autorate negotiation. Table 5– ...
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... Chapter 5: Signals Physical Layer Signals Transceiver Signals Table 5–6 lists the transceiver signals that are connected directly to the transceiver block. In many cases these signals must be shared by multiple transceiver blocks that are implemented in the same device Table 5–6. Transceiver Signals (Part Signal Direction ...
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... Refer to“Instantiating Multiple CPRI IP Cores” on page 2–4 channels—whether in two CPRI IP core instances CPRI IP core and in another component—in the same quad. In addition to customization of the transceiver through the transceiver parameter editor, you can use the transceiver reconfiguration block to dynamically modify the parameter interface ...
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... May 2011 Altera Corporation for details about the Avalon-MM interface. Description CPU clock signal. CPU peripheral reset. This reset is associated with the cpu_clk clock. cpu_reset can be asserted asynchronously, but must stay asserted at least one cpu_clk cycle and must be de-asserted synchronously with cpu_clk. Refer to Figure 4– ...
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... Table 5–8 and CPRI IP core. The CPRI MII interface is enabled if you turn off Include MAC block in the CPRI parameter editor. The CPRI MII interface signals are available only if you enable the CPRI MII interface. For information about the MII handshaking protocol ...
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... Ethernet HALT symbol in the data it passes to the CPRI link. Ethernet transmit nibble data. The data transmitted from the external Ethernet block to Input the CPRI IP core, for transmission on the CPRI link. This input bus is synchronous to cpri_mii_txd[3:0] the rising edge of the cpri_clkout clock. ...
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... CPRI MegaCore Function User Guide Direction Read-ready signal for each antenna-carrier interface. Indicates to the CPRI IP core that the data channel is ready to receive data on the next clock cycle. Asserted by the sink to mark ready cycles, which are Input cycles in which transfers can occur. If ready is asserted on cycle N, the cycle (N+READY_LATENCY ready cycle ...
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... Although each data channel has its own mapN_tx_ready signal, all data channels use the same map_tx_ready_thr threshold value. Indicates that the CPRI IP core is ready to receive data on the data channel in the current clock cycle. Asserted by the Avalon-ST sink to mark ready cycles, which are the cycles in which transfers can take place ...
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... The value is determined in the CPRI_IQ_TX_BUF_CONTROL register. Use this signal to disable external logic for inactive AxC interfaces and to map interface clock gating to save power. Table 5–13 list the signals on the CPRI IP core auxiliary interfaces. Table 5–12 through Table 5–13 are clocked by the internal clock ...
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... May 2011 Altera Corporation Bit Description cpri_rx_rfp: Synchronization pulse for start radio frame. The pulse occurs at the start of the radio frame on the CPRI receiver interface. cpri_rx_start: Indicates the start of the first basic frame on the AUX interface, and can be used by an AxC software application to trigger the AxC-specific resynchronization signal used in MAP synchronous buffer mode ...
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... Table 6–38 on page duration of the basic frame. cpri_tx_rfp: Synchronization pulse for start radio frame. The [0] pulse occurs at the start of the radio frame on the CPRI transmitter interface. Chapter 5: Signals Auxiliary Interface Signals Description 6–16. The signal is asserted for the May 2011 Altera Corporation ...
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... Synchronization input used in REC master to control the start of a new 10 ms radio frame. Asserting this signal resets the frame [64] synchronization machine. The CPRI IP core uses the rising edge of the pulse for synchronization. cpri_tx_aux_data: Data received on the AUX link, aligned with cpri_tx_seq with a delay of two cpri_clkout cycles ...
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... Signal Direction extended_rx_status_data Output [11:0] CPRI MegaCore Function User Guide Bits Description cpri_rx_los: CPRI receiver LOS indication (active high). This [11] bit reflects the value in the rx_los field of the CPRI_INTR register (Table 6–4 on page 6–2). cpri_rx_lcv: Current CPRI receiver 8B/10B line code violation [10:8] count in current clock cycle ...
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... Chapter 5: Signals Clock and Reset Interface Signals Clock and Reset Interface Signals Table 5–15 describes the CPRI IP core clock and reset signals not described in other sections with their associated modules. Table 5–15. CPRI IP Core Clock and Reset Signals Signal Direction Input ...
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... CPRI MegaCore Function User Guide Chapter 5: Signals Clock and Reset Interface Signals May 2011 Altera Corporation ...
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... The Altera CPRI IP core supports the following sets of registers that control the CPRI IP core or query its status: CPRI Interface Registers ■ ■ MAP Interface and AUX Interface Configuration Registers ■ Ethernet Registers ■ HDLC Registers All of the registers are 32 bits wide and their addresses are shown as hexadecimal values ...
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... CPRI Interface Registers This section lists the CPRI interface registers. the CPRI interface registers. registers in the CPRI IP core. Table 6–3. CPRI Interface Registers Memory Map Address 0x0 CPRI_INTR 0x4 CPRI_STATUS 0x8 CPRI_CONFIG 0xC CPRI_CTRL_INDEX 0x10 CPRI_RX_CTRL 0x14 CPRI_TX_CTRL 0x18 CPRI_LCV ...
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... Table 6–6. CPRI_CONFIG—CPRI Configuration—Offset: 0x8 (Part Field Bits Access [31:6] UR0 RSRV [5] RW tx_enable May 2011 Altera Corporation Access Function hw_reset interrupt enable. Controls whether a reset RW request received over the CPRI link raises an interrupt on the CPU IRQ line. CPRI interface module interrupt enable. RW The Ethernet and HDLC modules have separate interrupt enable control bits ...
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... Most recent received CPRI control word from CPRI hyperframe position Z.x.0, where x is the index in the cpri_ctrl_index field of the CPRI_CTRL_INDEX register. Chapter 6: Software Interface CPRI Interface Registers Default 3'h0 1'h0 1'h0 Default 24'h0 8'h0 Default 24'h0 8'h0 May 2011 Altera Corporation ...
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... RSRV [7] reset_gen_done_hold [6] reset_gen_done [5] reset_detect_hold [4] reset_detect May 2011 Altera Corporation Function Reserved. Control byte transmit enable. CPRI control byte to be transmitted in CPRI hyperframe position Z.x.0, where x is the index in the cpri_ctrl_index field of the CPRI_CTRL_INDEX register. Function Reserved. Number of line code violations (LCVs) detected in the 8B/10B decoding block in the transceiver. Enables CPRI link debugging. This register saturates at the value 255 ...
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... CPRI receiver clock and cpri_clkout (1) have different frequencies, as measured in the physical layer internal loopback path. Reserved. Chapter 6: Software Interface CPRI Interface Registers Default 1'h0 1'h0 1'h0 1'h0 “CPRI IP Core Default 27'h0 1’h0 2'h0 May 2011 Altera Corporation ...
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... Table 6–15. CPRI_CM_STATUS—CPRI Control and Management Status—Offset: 0x2C (Part Field Bits [31:12] UR0 RSRV [11] rx_slow_cm_rate_valid May 2011 Altera Corporation Function Physical layer loopback mode. The following values are defined loopback. 1: Full CPRI frame loop. Incoming CPRI data and control words are sent back as-is in outgoing CPRI communication ...
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... Note to Table 6–16: (1) WIDTH_RX_BUF is the value specified for the Receiver buffer depth parameter. This value is log it is set to six, specifying a 64-entry buffer. Altera recommends that you set it to four, specifying a 16-entry buffer, in slave configurations. CPRI MegaCore Function User Guide Access Function Accepted receive slow C& ...
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... RO Maximum value Current byte-alignment delay. Access Function Reserved. Measured round trip delay from cpri_tx_rfp to RO cpri_rx_rfp. Unit is cpri_clkout clock periods. Function Reserved. Integration period for extended delay measurement. Program this field with the user-defined value N, where M/N = clk_ex_delay period / cpri_clkout period. Refer to Receive Buffer Delay Calculation Example” ...
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... CPRI line rate to be used in next attempt to achieve frame synchronization. You set the line rate in your implementation of the autorate negotiation hardware and software outside the CPRI IP core. Refer to Appendix B, Implementing CPRI Link Autorate Negotiation, for information about how to use the autorate negotiation logic implemented in the CPRI IP core ...
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... Table 6–25. CPRI_TX_PROT_VER— Tx Protocol Version —Offset: 0x58 Field Bits [31:8] RSRV [7:0] tx_prot_version May 2011 Altera Corporation Access Function Indicates a hw_reset interrupt is pending (the interrupt occurred but is not yet serviced slave, this bit is set when a reset request is detected in incoming CPRI communication at Z.130.0, but neither the ...
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... Received scrambler seed. The receiver descrambles the RO incoming CPRI communication based on this seed. Chapter 6: Software Interface CPRI Interface Registers Default 1’h0 31’h0 Default 1’h0 31’h0 May 2011 Altera Corporation ...
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... MAP Interface and AUX Interface Configuration Registers This section lists the MAP interface configuration registers. memory map for the MAP interface configuration registers. Table 6–45 describe the MAP interface configuration registers in the CPRI IP core. Table 6–28. CPRI MAP Interface Configuration Registers Memory Map Address 0x100 ...
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... Rx and Tx tables. The value in this RW field determines the table entries that appear in the CPRI_MAP_TBL_RX and CPRI_MAP_TBL_TX registers. Chapter 6: Software Interface Default 2’h0 (Note 1) Default 19’h0 5’h0 3’h0 5’h0 Default 0 0 (Note 1) Default 21’h0 11’h0 May 2011 Altera Corporation ...
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... RW map_rx_offset_x Table 6–36. CPRI_MAP_OFFSET_TX—MAP Tx Frame Offset—Offset: 0x11C (Part Field Bits Access [31:17] UR0 RSRV [16] RW map_tx_hf_resync May 2011 Altera Corporation Access Function UR0 Reserved. RW Starting bit position of IQ sample in timeslot. UR0 Reserved. RW AxC interface number. UR0 Reserved. ...
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... CPRI frame buffer to be prepared for transmission on the CPRI link. Basic frame number for start of read of CPRI MAP transmitter AxC container block from each enabled mapN Tx buffer. The CPRI IP core reads the data from the mapN Tx buffer and routes it to the CPRI frame buffer to be prepared for transmission on the CPRI link ...
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... Table 6–43: (1) If this CPRI IP core has more than 16 antenna-carrier interfaces (N_MAP > 16), the status for antenna-carrier interfaces 0 through the register at offset 0x140, and the status for antenna-carrier interfaces 16 and the register at offset 0x144. The maximum number of antenna-carrier interfaces in the CPRI IP core is 24. ...
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... Table 6–46: (1) If this CPRI IP core has more than 16 antenna-carrier interfaces (N_MAP > 16), the status for antenna-carrier interfaces 0 through the register at offset 0x180, and the status for antenna-carrier interfaces 16 and the register at offset 0x184. The maximum number of antenna-carrier interfaces in the CPRI IP core is 24. ...
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... RO rx_length [2] RO rx_abort [1] RO rx_eop [0] RO rx_ready May 2011 Altera Corporation Name Ethernet Receiver Module Status Ethernet Transmitter Module Status Ethernet Feature Configuration 1 Ethernet Feature Configuration 2 Ethernet Rx Control Ethernet Rx Data Ethernet Rx Data With Wait-State Insertion Ethernet Tx Control Ethernet Tx Data Ethernet Tx Data With Wait-State Insertion ...
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... RO Reserved. Chapter 6: Software Interface Ethernet Registers Default 29'h0 1’h0 1’h0 1’h0 Default 11'h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 2’h0 1’h0 1'h0 May 2011 Altera Corporation ...
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... RSRV [3:2] WO tx_length [1] WO tx_discard [0] WO tx_eop May 2011 Altera Corporation Function Reserved. Enables insertion of Ethernet frame check sequence (FCS) at the end of the Ethernet frame. Function Reserved. Indicates that the Ethernet receiver module should discard the current Ethernet Rx frame. Function Ethernet Rx frame data. If the Ethernet receiver module takes Ethernet data from this register, if data is not ready when the module expects it, the Ethernet receiver module aborts the packet ...
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... Transmit store-and-forward mode. In store-and-forward mode, a full packet is stored in the Tx buffer before transmission starts. Packets longer than the Tx buffer are aborted. Chapter 6: Software Interface Ethernet Registers Default 1'h0 Default 1'h0 Default 16'h0 16'h0 Default 32'h0 Default 32'h0 Default 15’h0 16’h0004 1'h0 May 2011 Altera Corporation ...
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... HDLC Registers This section lists the HDLC registers. HDLC registers. CPRI IP core you turn off the Include MAC block parameter, your application cannot access the HDLC registers. In that case, attempts to access these registers read zeroes and do not write successfully, as for a Reserved register address. ...
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... HDLC Tx interrupt enable. RW HDLC Rx interrupt enable. RW HDLC global interrupt enable. Chapter 6: Software Interface HDLC Registers Default 2’h0 1’h0 1’h0 1’h0 Default 29'h0 1’h0 1’h0 1’h0 Default 11'h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 1’h0 May 2011 Altera Corporation ...
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... RO rx_data Table 6–72. HDLC_RX_DATA_WAIT—HDLC Rx Data with Wait-State Insertion—Offset: 0x318 Field Bits Access [31:0] RO rx_data May 2011 Altera Corporation Access Function Enable reception of Rx HDLC frames longer than 1536 RW bytes. UR0 Reserved. Indicates that a length check is performed on Rx packets, RW and those with length less than 64 bytes are discarded ...
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... Transmit store-and-forward mode. In store-and-forward mode, a full packet is stored before transmission starts. Packets longer than the Tx buffer are aborted. Chapter 6: Software Interface HDLC Registers Default 28'h0 1’h0 1'h0 1’h0 Default 1'h0 Default 1'h0 Default 25'h0 6'h0 Default 15’h0 16’h0004 1'h0 May 2011 Altera Corporation ...
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... Table 6–78. HDLC_CNT_RX_FRAME—HDLC Receiver Module Frame Counter—Offset: 0x330 Field Bits [31:0] hdlc_cnt_rx_frame Table 6–79. HDLC_CNT_TX_FRAME—HDLC Transmitter Module Frame Counter—Offset: 0x334 Field Bits [31:0] hdlc_cnt_tx_frame May 2011 Altera Corporation Access Function RO Number of frames received from the CPRI receiver. Access Function RO Number of frame transmitted to the CPRI transmitter. 6–27 ...
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... CPRI MegaCore Function User Guide Chapter 6: Software Interface HDLC Registers May 2011 Altera Corporation ...
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... Each testbench consists of a CPRI IP core and a testbench that initializes the CPRI IP core and sends the generated data to the CPRI IP core interfaces listed in the testbenches, the CPRI IP core’s high-speed transceiver output is looped back to its high-speed transceiver input. The testbench module provides clocking, reset, and initialization control, and processes to write to and read from the IP core’ ...
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... Stratix IV GX device, and tb_altera_cpri_c4gx_autorate.vhd, which targets a Cyclone IV GX device. Figure 7–1. CPRI IP Core Non-MII Interface Demonstration Testbench (tb_altera_cpri.vhd) tb_altera_cpri Altera Testbench Figure 7–2. CPRI IP Core MII Interface Demonstration Testbench (tb_altera_cpri_mii.vhd) tb_altera_cpri_mii Altera Testbench CPRI MegaCore Function User Guide illustrate the autorate negotiation testbenches, ...
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... Chapter 7: Testbenches Figure 7–3. CPRI IP Core MII Interface No IQ Demonstration Testbench (tb_altera_cpri_mii_noiq.vhd) tb_altera_cpri_mii_noiq Altera Testbench Figure 7–4. CPRI IP Core Autorate Negotiation Demonstration Testbench (tb_altera_cpri_autorate.vhd) tb_altera_cpri_autorate Altera Testbench May 2011 Altera Corporation Reference Clock MII Interface gxb_txdataout gxb_rxdatain aux_tx_status_data, Avalon-ST aux_rx_status_data Tx AUX Interface ...
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... After coming out of the reset state, the CPRI IP core starts the frame synchronization process to detect the presence of a partner and establish frame synchronization. The tb_altera_cpri, tb_altera_cpri_mii, and tb_altera_cpri_mii_noiq testbenches then perform the following actions: Sends a predetermined data sequence to the AUX interface, and checks that the ■ ...
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... When these values appear in the waveform display, the CPRI link is up and ready to receive and send data. Next, basic programming of the internal registers is performed in the DUT to allow CPRI communication. tb_altera_cpri and tb_altera_cpri_mii DUTs. For a full description of each register, refer to Chapter 6, Software Table 7–3. Testbench Registers ...
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... In the Quartus II software, create a Quartus II project using the New Project Wizard available from the File menu. The project targets the same device as your intended DUT. Refer to 2. Generate the CPRI IP core DUT instance with the properties shown in Table 7–4. MegaWizard Plug-In Manager Options for CPRI IP Core DUT Parameter ...
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... This folder contains the testbench VHDL (.vhd) files and the .do files to run the testbenches text editor, open the tb_altera_cpri_<variant>.vhd testbench file for the testbench you want to run. c. Locate the definition of the constant DEVICE. A comment located with the constant definition describes a correspondence between values and device families ...
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... The input to and subsequent output data from each of the AUX, map0, and MII interfaces is visible in the waveform for testbenches that have the relevant interface. CPRI MegaCore Function User Guide Chapter 7: Testbenches Running the Testbenches May 2011 Altera Corporation ...
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... The cpri_rx_bfn_state output signal appears on extended_rx_status_data[6]. The CPRI IP core can now receive and transmit data on the CPRI link, on the antenna-carrier interfaces, and on the auxiliary AUX interface. To access the registers, the system requires an Avalon-MM master, for example a Nios II processor ...
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... A–2 CPRI MegaCore Function User Guide Appendix A: Initialization Sequence May 2011 Altera Corporation ...
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... The CPRI IP core supports autorate negotiation. This feature allows you to specify that the CPRI IP core should determine the CPRI line rate at startup dynamically, by stepping down to successively slower line rates if the low-level receiver cannot achieve frame synchronization with the current line rate. You can provide input to the low-level CPRI interface receiver to implement this capability in your design, with the help of logic connected outside the CPRI IP core ...
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... Stratix IV GX device. However, if you remove the options for the two highest CPRI line rates, the examples are functional for Cyclone IV GX devices. The examples clarify the functionality provided by the CPRI IP core, and the logic and data you must configure in your design outside the CPRI IP core. ...
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... CPRI IP core must perform certain steps to activate the autorate negotiation support logic in the CPRI IP core. This section describes these steps. To start autorate negotiation in your CPRI IP core, in addition to its own initialization outside the CPRI IP core, your hardware and software must perform the following steps: 1 ...
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... B–4 2. Set the logic that feeds the gxb_refclk input to the CPRI IP core to the correct value for the next CPRI line rate at which you want to try to achieve frame synchronization. 3. Configure the ALTGX_RECONFIG megafunction with the .mif file for the desired CPRI line rate. ...
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... Select the .qpf file and click Open. 5. Open the existing IP core for editing in the MegaWizard Plug-In Manager your CPRI IP core slave configuration, set Receiver buffer depth Click Finish. 8. Before you simulate and compile your new design, ensure that you connect the new cpu_byteenable[3:0] input signal to appropriate logic ...
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... C–2 CPRI MegaCore Function User Guide Appendix C: Porting a CPRI IP Core from the Previous Version of the Software May 2011 Altera Corporation ...
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... MAP interface and to demonstrate autorate negotiation. February 2010 9.1 SP1 Initial release. May 2011 Altera Corporation Additional Information Changes Made to match individual register addresses as updated for v10.1. Appendix C, Porting a CPRI IP Core from the Previous Version of the Software. CPRI MegaCore Function User Guide ...
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... GUI. Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file. Indicate document titles. For example, Stratix IV Design Guidelines. Indicates variables. For example ...
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... A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center website, where you can sign up to receive update notifications for Altera documents. Info–3 page of the Altera ...
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... Info–4 CPRI MegaCore Function User Guide Additional Information Typographic Conventions May 2011 Altera Corporation ...