IP-CPRI Altera, IP-CPRI Datasheet - Page 122

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–26
Table 6–73. HDLC_TX_CONTROL—HDLC Tx Control—Offset: 0x31C
Table 6–74. HDLC_TX_DATA—HDLC Tx Data—Offset: 0x320
Table 6–75. HDLC_TX_DATA_WAIT—HDLC Tx Data with Wait-State Insertion—Offset: 0x324
Table 6–76. HDLC_RX_EX_STATUS—HDLC Rx Additional Status—Offset: 0x328
Table 6–77. HDLC_CONFIG_3—HDLC Feature Configuration 3—Offset: 0x32C
CPRI MegaCore Function User Guide
RSRV
tx_length
tx_discard
tx_eop
tx_data
tx_data
RSRV
CRC_error
RSRV
RSRV
tx_start_thr
tx_st_fwd
Field
Field
Field
Field
Field
[31:17] UR0
[16:1]
[0]
[31:4] UR0
[3:2]
[1]
[0]
[31:0] RW
[31:0] RW
Bits
Bits
Bits
Bits
[31:7]
[6]
[5:0]
Bits
RW
WO
RW
RW
RW
Access
Access
Access
Access
UR0
RC
UR0
Access
Reserved.
Length of the final word in the packet. Values are:
This field is valid when the tx_eop bit is asserted.
Indicates that the HDLC transmitter module should discard the
current HDLC Tx frame.
Indicates that the next data word to be written to the HDLC_TX_DATA
or HDLC_TX_DATA_WAIT register contains the end-of-packet byte for
this Tx packet.
HDLC Tx frame data. If the HDLC transmitter module writes HDLC
data to this register, if data is not ready when the module expects it,
the HDLC transmitter module aborts the packet.
HDLC Tx frame data. If the HDLC transmitter module writes HDLC
data to this register, it waits until data is ready, unless the CPU times
out the operation.
Reserved.
Transmit start threshold. If store-and-forward mode is disabled,
transmission to the CPRI link starts when this number of 32-bit
words are stored in the Tx buffer.
Transmit store-and-forward mode. In store-and-forward mode, a
full packet is stored before transmission starts. Packets longer
than the Tx buffer are aborted.
00: 1 valid byte
01: 2 valid bytes
10: 3 valid bytes
11: 4 valid bytes
Reserved.
Indicates that an HDLC frame with a CRC error was received. 1'h0
Reserved.
Function
Function
Function
Function
Function
December 2010 Altera Corporation
Chapter 6: Software Interface
25'h0
6'h0
HDLC Registers
15’h0
16’h0004
1'h0
Default
Default
28'h0
1’h0
1'h0
1’h0
1'h0
1'h0
Default
Default
Default