IP-CPRI Altera, IP-CPRI Datasheet - Page 66

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–42
CPRI MegaCore Function User Guide
2. Delay from the CPRI low-level receiver block to the MAP interface block. This
3. Delay from arrival of the data at the MAP interface block, through an AxC
The following sections describe the individual delays and how to calculate them.
Transceiver Latency
The Altera high-speed transceiver is implemented using the deterministic latency
protocol, which ensures that delays in comma alignment and in byte alignment within
the transceiver are consistent.
Table 4–6
sides of the CPRI MegaCore function. These values correspond to T_txv_RX and
T_txv_TX in
Table 4–6. Fixed Latency Through Transceiver
The clean-up PLL shown in
Figure 4–6 on page 4–11
the gxb_pll_inclk signal, to ensure frequency match. To preserve the T_txv_RX
latency in
contains no asynchronous dividers.
Extended Rx Delay Measurement
The second component of the link delay is the delay through the CPRI Receive buffer.
The latency of the CPRI Receive buffer depends on the number of 32-bit words
currently stored in the buffer, and the phase difference between the recovered receive
clock, which is used to write data to the buffer, and the system clock cpri_clkout,
which is used to read data from the buffer. The CPRI MegaCore function uses a
dedicated clock, clk_ex_delay, to measure the Rx buffer delay to your desired
precision. The rx_ex_delay field of the CPRI_EX_DELAY_CONFIG register contains the
value N, such that N clock periods of the clk_ex_delay clock are equal to some whole
In CPRI Receiver (T_txv_RX)
In CPRI Transmitter (T_txv_TX)
Note to
(1) The deterministic latency mode of the Cyclone IV GX device transceivers is still pending characterization.
delay is also identical to the delay in the path to the AUX interface. Refer to
Core Delay Component” on page
interface and out to its data channel. This delay comprises the time during which
the data waits in the mapN Rx buffer. When the AxC interfaces are in synchronous
buffer mode, the timing depends on the offset values in the CPRI_START_OFFSET_RX
and CPRI_MAP_OFFSET_RX registers and on the application response to the
cpri_rx_start output signal. When the AxC interfaces are in FIFO mode, the
delay depends on the programmed buffer threshold and the application. Refer to
“CPRI MAP Receiver Interface” on page
Table
shows the fixed latency through the transceiver in the receive and transmit
Table
Direction
4–6:
Figure
4–6, you must ensure that the reference clock to the clean-up PLL
4–19.
uses the recovered clock as input to the PLL that generates
Figure 4–2 on page
Arria II GX or Cyclone IV GX
Latency Through Transceiver in cpri_clkout Clock Cycles
4–44.
Device
4.65
3.35
4–29.
(1)
4–7,
Figure 4–4 on page
December 2010 Altera Corporation
Chapter 4: Functional Description
Arria II GZ or Stratix IV GX
Device
6.5
3.5
Delay Measurement
4–9, and
“Fixed