IP-CPRI Altera, IP-CPRI Datasheet - Page 28

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–4
Clocking and Reset Structure
CPRI MegaCore Function User Guide
MII Interface
MegaCore Function Basic Clock Domains
f
determines the IQ sample data to pass to other REs to support multi-hop network
configurations or to bypass the CPRI MegaCore function MAP interface to implement
custom mapping algorithms outside the MegaCore function. The CPRI MegaCore
function implements the AUX interface as one incoming and one outgoing Avalon-ST
interface.
For more information about how this interface functions with the CPRI MegaCore
function, refer to
For information about the Avalon-ST interface, refer to
The MII interface allows the CPRI MegaCore function to communicate directly with
an external Ethernet MAC block, bypassing the internal Ethernet and HDLC
implementation that communicates through the CPU Interface. You specify in the
CPRI parameter editor whether to implement this interface or to use the Ethernet or
HDLC MAC block available with the CPRI MegaCore function. If you configure the
CPRI MegaCore function with the MII interface, you must implement the Ethernet
MAC block outside the CPRI MegaCore function. For more information, refer to
Interface to an External Ethernet Block” on page
The CPRI MegaCore function has a variable number of clock domains, depending on
the number of antenna-carrier interfaces. In addition to the high-speed clock domains
inside the Arria II GX, Arria II GZ, Cyclone IV GX, or Stratix IV GX transceiver, the
CPRI MegaCore function contains three basic clock domains, two clock domains for
the MII interface if it is implemented, and two clock domains for each antenna-carrier
interface.
You can configure a CPRI MegaCore function in master or slave clocking mode. REC
configurations and RE master configurations use master clocking mode, and RE slave
configurations use slave clocking mode.
The top-level blocks shown in
domain boundaries. The clocking diagrams in
page 4–10
Each CPRI MegaCore function has the following three basic clock domains:
■
■
■
cpri_clkout—Main clock for the CPRI MegaCore function. This clock is derived
from the transceiver transmit PLL, and its frequency depends on the CPRI line
rate. For more information about this correspondence, refer to
Communication Link Line Rates” on page
clk_ex_delay—Clock for extended delay measurement. For more information
about this clock, refer to
cpu_clk—Clock that controls the input to the CPU interface of the CPRI MegaCore
function and drives the CPU interface module.
show the details.
“Auxiliary Interfaces” on page
“Extended Rx Delay Measurement” on page
“Architecture Overview” on page 4–2
Figure 4–2 on page 4–7
4–12.
4–33.
4–52.
Avalon Interface
December 2010 Altera Corporation
Chapter 4: Functional Description
Clocking and Reset Structure
“CPRI
define the clock
to
Specifications.
Figure 4–5 on
4–42.
“MII