XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 88

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Appendix A: Optional Power-of-2 Addressing Mode
Permanently Changing to the Power-of-2 Addressing Mode
Power-of-2 Addressing Mode
88
To permanently change over from the
2 addressing mode, the programmer or FPGA application must perform the following
steps.
•
•
Table A-2: Power-of-2 Page Size Command Sequence
•
•
•
•
If the FPGA is powered-down before the completion of the program cycle, then the Power-
of-2 address setting cannot be guaranteed. Should this occur, however, check that the
Size
successfully programmed. If not, re-issue the Power-of-2 Page Size command.
All Spartan-3AN FPGAs are shipped supporting the
optional Power-of-2 Addressing mode is only available after
Power-of-2 Addressing
MOSI
Pin
Drive CSB Low while CLK is High, or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the Power-of-2 Page Size command
sequence, shown in
After clocking in the last bit of the command sequence, set CSB High to start the
internally self-timed programming cycle.
Wait at least the Page Programming time, T
specified in the
bit (bit 7) is ‘0’ in the
operation is in progress.
After the programming operation completes, the FPGA power supplies must be
cycled off, then reapplied before the Power-of-2 addressing mode becomes active.
Any data stored in the ISF memory prior to setting the Power-of-2 addressing mode
will be corrupted. Erase and reprogram the ISF memory with the intended data.
bit (bit 0) is set to ‘1’ in the
Byte 1
0x3D
Spartan-3AN FPGA data
Mode.
Table
Status
www.xilinx.com
A-2, most-significant bit first.
Status
Register, indicating that an ISF memory programming
Four-byte Command Sequence
Byte 2
0x2A
Default Addressing Mode
Register, indicating that the page size was
sheet. During this time, the
PP
., shown in
Spartan-3AN In-System Flash User Guide
Default Addressing
Byte 3
0x80
Permanently Changing to the
Table 4-5, page 44
UG333 (v2.1) January 15, 2009
to the optional power-of-
READY/BUSY
Mode. The
Byte 4
0xA6
and
Page
R