XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 32

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Read Commands
Table 3-3: Random Read (0x03) Command Summary
32
MOSI
MISO
Notes:
1. The Random Read command is supported in simulation.
MOSI
MISO
CSB
CLK
Pin
CSB remains Low throughout entire transfer
Command
0
0 0 0 0 0 0 1 1
Command Code (0x03)
Figure 3-3: Random Read Command Waveform (XC3S700AN, Default Address Mode)
Byte 1
0x03
1
2
3
4
5
Default Addressing: See
Optional Power-of-2 Addressing: See
6
To perform a Random Read command, summarized in
Figure
•
•
•
•
•
•
The CSB signal must remain Low throughout the entire data transfer
command code, the 24 address bits, and when reading the data bytes.
High Address
7
Byte 2
8
0 0 0
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the Random Read command code, 0x03,
most-significant bit first.
Similarly, serially clock in a 24-bit starting byte address.
♦
♦
♦
No dummy byte is required for the Random Read command. At this point, the data
supplied on the MOSI input does not matter.
On the next falling CLK edge, the requested data serially appears on the MISO output
port.
♦
♦
To end the data transfer, deassert CSB High on the falling edge of CLK.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Address High Byte
3-3, the FPGA application must perform the following actions.
24-bit Starting Page and Byte Address
The starting byte location can be anywhere in the ISF memory array, located on
any page, as shown in
If using the default address scheme, see
If using power-of-2 addressing, see
Data is clocked out serially, most-significant bit first.
While CSB is Low, new data appears on the MISO output on every subsequent
falling CLK edge. The ISF memory automatically increments the implied address
counter through contiguous memory locations, as highlighted in
regardless of the address mode.
High
Middle Address
Table 2-2, page 19
Byte 3
Address Middle Byte
www.xilinx.com
Figure
Table A-3, page 89
3-1.
Low Address
Byte 4
Address Low Byte
Spartan-3AN FPGA In-System Flash User Guide
Table A-3, page 89
Table 2-2, page 19
Table 3-3
Data Byte +0
MSB
Byte 5
(most-significant bit first)
ISF Memory Data Bytes
XX
.
UG333 (v2.1) January 15, 2009
First Data Byte
and shown in detail in
.
Don’t Care
—
...
...
when writing the
Figure
LSB MSB
Data Byte +n
40 41
UG333_c3_02_020807
Byte n+5
XX
3-1,
42
R