XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 76

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8: Sector-Based Program/Erase Protection
Table 8-6: Sector Protection Register Program Command Sequence
76
MOSI
Pin
Byte 1
0x3D
Four-byte Command Sequence
Sector Protection Register Program
Byte 2
0x2A
Table 8-5: Sector Protection Register Erase Command Sequence
•
A Low-to-High transition on the CSB input completes the command sequence and the ISF
memory then erases the Sector Protection Register. The erase operation is internally self-
timed and completes in the Page Erase time, T
in the
Status Register
progress or whether it has completed.
If the FPGA V
the content of the
The
disabled. The erased state of each byte in the Sector Protection Register is 0xFF, which
protects each sector. Leave sector protection enabled while erasing of the Sector Protection
Register, which then prevents accidental programming or erasing of the device. If the
FPGA application should issue an erroneous program or erase command immediately
after erasing the Sector Protection Register and before the register is reprogrammed, then
the erroneous program or erase command is prevented.
Once the
Protection Register Program command sequence.
To issue the Sector Protection Register Program command sequence, the FPGA application
must perform the following actions using the SPI_ACCESS design primitive.
•
•
•
MOSI
Pin
Byte 3
After clocking in the last bit of the command sequence, deassert the CSB pin High.
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the four-byte Sector Protection Register
Program command sequence shown in
of each byte first.
0x7F
After clocking in the last bit of the command sequence, send the
Register
♦
Sector Protection Register
Spartan-3AN FPGA data
The number of bytes depends on the Spartan-3AN FPGA, as highlighted in
Table 8-6
Sector Protection Register
Byte 4
programming data on the MOSI pin.
0xFC
CCAUX
Byte 1
0x3D
indicates whether the Sector Protection Register Erase operation is in
and
Sector Protection Register
power supply is interrupted before the erase cycle completes, then
Sector 0
Sector Protection Register Value (byte locations corresponds to sector)
Table 8-3, page
Byte 5
www.xilinx.com
can be erased regardless if sector protection is enabled or
XC3S50AN (4 bytes)
sheet. During this time, the
XC3S200AN, XC3S400AN (8 bytes)
Sector 1
Byte 6
Four-byte Command Sequence
Byte 2
0x2A
is erased, reprogram the register using the Sector
XC3S700AN, XC3S1400AN (16 bytes)
75.
Sector 2
Byte 7
Table 8-6
Spartan-3AN FPGA In-System Flash User Guide
is not guaranteed.
PE
, shown in
Sector 3
on the MOSI pin, most-significant bit
Byte 8
Byte 3
0x7F
Table 5-4, page 53
READY/BUSY
UG333 (v2.1) January 15, 2009
...
...
Byte 12
Sector 7
Sector Protection
bit (bit 7) of the
and specified
Byte 4
0xCF
...
...
Sector 15
Byte 20
R