XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet
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Spartan-3AN FPGA In-System Flash User Guide For Spartan®-3AN FPGA applications that read or write data to or from the In-System Flash memory after configuration UG333 (v2.1) January 15, 2009 R ...
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...
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Table of Contents Chapter 1: Overview and SPI_ACCESS Interface In-System Flash Summary Accessing In-System Flash Memory After Configuration SPI_ACCESS Design Primitive . . . . . . . . . . . . . . . . . . . ...
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Auto Page Rewrite Chapter 5: Erase Commands Sector Protect and Sector Lockdown Prevent Erase Operations Erased State . . . . . . . . . . . . . . . . . . . . . . . ...
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R Chapter 9: Security Register Security Register Security Register Program Security Register Read Appendix A: Optional Power-of-2 Addressing Mode How to Determine the Current Addressing Mode Permanently Changing to the Power-of-2 Addressing Mode Power-of-2 Addressing Mode Power-of-2 Addressing . . ...
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Spartan-3AN In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
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R Overview and SPI_ACCESS Interface Note: This user guide only applies to Spartan system Flash after configuration. This user guide is not required for applications that only use the in- system Flash to configure the FPGA. For Spartan-3AN FPGA configuration ...
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Chapter 1: Overview and SPI_ACCESS Interface Table 1-1: In-System Flash Memory Summary Description In-System Flash (ISF) memory bits SRAM page buffers Default Addressing Mode page size (bytes) Optional Power-of-2 Addressing Mode Pages Blocks Sectors Pages per Block Pages per Sector ...
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R Accessing In-System Flash Memory After Configuration SPI_ACCESS Design Primitive After the FPGA configures, the application loaded into the FPGA can access the ISF memory using a special design primitive called SPI_ACCESS, shown in data accesses to and from the ...
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Chapter 1: Overview and SPI_ACCESS Interface Table 1-3: SPI_ACCESS Primitive Attributes (Continued) Attribute Type Allowed Values SIM_MEM_FILE String Specified file and directory name SIM_FACTORY_ID 64-byte Any 64-byte Hex Hex Value Value SIM_DELAY_TYPE String “ACCURATE”, “SCALED” HDL Instantiation Examples The SPI_ACCESS ...
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R CSB CLK ); -- End of SPI_ACCESS_inst instantiation Verilog Using Verilog, simply connect the SPI_ACCESS design primitive to signal names within the FPGA application. SPI_ACCESS #( .SIM_DEVICE("3S700AN") ) SPI_ACCESS_inst ( .MISO(MISO_signal), .MOSI(MOSI_signal), .CSB(CSB_signal), .CLK(CLK_signal End of SPI_ACCESS_inst ...
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Chapter 1: Overview and SPI_ACCESS Interface • The FPGA application selects the ISF memory by driving the SPI_ACCESS CSB input Low when the CLK input is High and de-selects the ISF memory by driving the CSB input High. • When ...
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R 1. The FPGA application starts the command by driving the SPI_ACCESS CSB input Low, while the CLK input is High. Subsequently, the CSB input must remain Low throughout the entire transfer. 2. The Status Register Read mentioned in Consequently, ...
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Chapter 1: Overview and SPI_ACCESS Interface Table 1-4: SPI_ACCESS Simulation Supported Commands (Continued) Command Common Application Buffer to Page First erases selected memory page and programs page with data from Program with Built- designated buffer in Erase Buffer to Page ...
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R In-System Flash Memory Architecture Block Diagram The Spartan reprogrammable Flash memory array and one or two SRAM page buffers, as shown in Figure 2-1. The Flash memory array is organized into Pages, Blocks, and Sectors. The smallest erasable unit ...
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... Sector 0 Table 2-1: Spartan-3AN FPGA Memory Architecture Device XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN The most basic construct within the hierarchy is a memory Page. By default, a Page consists of 264 bytes, except on the XC3S1400AN FPGA, which has a larger page size of 528 bytes. The page size is reduced when the shown in gray in enough to hold an entire page image ...
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R Sector 0 is further subdivided into two, individually protected sub-sectors, as shown in Figure 2-3. While the combined Sector 0 is the same size as all other sectors, Sector 0a is always 8 pages while Sector 0b represents the ...
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Chapter 2: In-System Flash Memory Architecture • Counters, to track the number of program/erase cycles per page. Sector Address Block Address Page Address Figure 2-4: Default Addressing Mode for ...
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R Default Addressing Mode In the default addressing mode, specific memory bytes are addressed by page and by the specific byte location within that page. As shown in page size varies by FPGA part number. Table 2-2: Default Addressing Mode ...
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... ISF memory allocation for the XC3S50AN FPGA is provided in • ISF memory allocation for the XC3S200AN FPGA is provided in • ISF memory allocation for the XC3S400AN FPGA is provided in • ISF memory allocation for the XC3S700AN FPGA is provided in • ISF memory allocation for the XC3S1400AN FPGA is provided in 20 “ ...
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R Table 2-3: XC3S50AN In-System Flash Memory Allocation Allocation Bitstream First available user data space (page aligned) 2nd MultiBoot Bitstream, or available for user data space Second available user data space (page aligned) Spartan-3AN FPGA In-System Flash User Guide UG333 ...
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Chapter 2: In-System Flash Memory Architecture Table 2-4: XC3S200AN In-System Flash Memory Allocation Allocation Bitstream First available user data space (page aligned) 2nd MultiBoot Bitstream, or available for user data Second available user data space (page aligned) User data space ...
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... R Table 2-5: XC3S400AN In-System Flash Memory Allocation Allocation Bitstream First available user data space (page aligned) 2nd MultiBoot Bitstream, or available for user data Second available user data space (page aligned) Spartan-3AN FPGA In-System Flash User Guide UG333 (v2.1) January 15, 2009 Default Addressing ...
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Chapter 2: In-System Flash Memory Architecture Table 2-6: XC3S700AN In-System Flash Memory Allocation Allocation Bitstream First available user data space (page aligned) 2nd MultiBoot Bitstream, or available for user data Second available user data space (page aligned) User data space ...
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R Table 2-7: XC3S1400AN In-System Flash Memory Allocation Allocation Bitstream First available user data space (page aligned) 2nd MultiBoot Bitstream, or available for user data Second available user data space (page aligned) User data space (sector aligned) Spartan-3AN FPGA In-System ...
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Chapter 2: In-System Flash Memory Architecture MultiBoot Configuration Bitstream Guidelines The following guidelines are recommended when storing multiple configuration files in the In-System Flash (ISF) memory. Align to Flash Sector Boundaries Spartan-3AN FPGA MultiBoot addressing is flexible enough to allow ...
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R User Data Storage Guidelines The following guidelines are recommended when storing user data in the In-System Flash (ISF) memory not intermix user data with the last page of FPGA configuration bitstream data. Intermixing user data and configuration ...
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Chapter 2: In-System Flash Memory Architecture 28 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
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R Read Commands The Spartan directly from the main Flash memory or from either one of the SRAM data buffers by issuing the appropriate command code. supported read commands. Some read commands offer multiple forms. One form is best for ...
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Chapter 3: Read Commands Fast Read The Fast Read command is best for longer, sequential read operations. This is the same command that the FPGA issues during configuration. This command is also best for code shadowing applications, where the FPGA ...
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R • Similarly, serially clock in a 24-bit page and byte starting address. ♦ The starting byte location can be anywhere in the ISF memory array, located on any page, as shown in ♦ If using default addressing, see ♦ ...
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Chapter 3: Read Commands To perform a Random Read command, summarized in Figure 3-3, the FPGA application must perform the following actions. Table 3-3: Random Read (0x03) Command Summary 24-bit Starting Page and Byte Address Command High Address Pin Byte ...
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R Upon reaching the end of a memory page, the ISF memory continues reading at the beginning of the next page, as shown in a page boundary. After reading the last bit in the memory array, the ISF continues reading ...
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Chapter 3: Read Commands Table 3-4: Page to Buffer Transfer Command Summary Command Pin Byte 1 Page to Buffer 1 Default Addressing: See Transfer Power-of-2 Addressing: See 0x53 MOSI Page to Buffer 2 (1) Transfer 0x55 Notes: 1. The Buffer ...
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R Buffer Read The FPGA application can independently access the SRAM data buffers separately from the ISF memory array, as shown in reads data directly from the selected buffer. When reading data from the buffer, first load data into the ...
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Chapter 3: Read Commands The slower version that operates MHz, shown in single, randomly-accessed bytes within the SRAM page buffer. This version has lower initial latency for single-byte transfers. Table 3-7: Buffer Read Command Summary (Low Frequency, ...
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R ♦ If using the default address scheme, see ♦ If using power-of-2 addressing, see • The slower version of the command while the faster version bits. At this point, the data supplied on the MOSI input does not matter. ...
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Chapter 3: Read Commands 38 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
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R Write and Program Commands The Spartan memory either directly to the main Flash memory array or through one of the SRAM page buffers by issuing the appropriate command code. various supported write and program commands. One form is best ...
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Chapter 4: Write and Program Commands Table 4-1: Summary of Write and Program Commands (Continued) Command Best Application Refresh page Auto Page Rewrite contents after 10,000 random program Buffer 2 operations to a sector Notes: 1. The Buffer 2 commands ...
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R Table 4-2: Buffer Write Command Summary High Address Command Unused Pin Byte 1 Byte 2 Buffer 1 Write 0x84 MOSI 0x00 (1) Buffer 2 Write 0x87 Notes: 1. The Buffer 2 Write command is not available in the XC3S50AN ...
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Chapter 4: Write and Program Commands Buffer 1 to Page Program with Erase MOSI MISO CSB CLK Buffer 2 to Page Program with Erase • The Buffer to Page Program without Built-in Erase command, shown in simply programs an erased ...
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... Page Erase and Programming Time www.xilinx.com 24-bit Page Address Middle Address Low Address Byte Address Unused Byte 3 Byte 4 Don’t Care XX Table 2-2, page 19 or Table 5-3, page 89. and specified in the Spartan-3AN PEP FPGA Typ Max Units XC3S50AN XC3S200AN 14 35 XC3S400AN XC3S700AN XC3S1400AN ...
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... The Page Program Through Buffer command is supported in simulation shown in Table 4-5 and specified in the PP PP Description Page Programming Time XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN READY/BUSY Buffer Write (Figure 4-2) operations. The FPGA application must specify a full 24-bit Table 4-2, most-significant bit first. Low Address Byte 3 Byte 4 ...
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R • Similarly, serially clock in a 24-bit starting page and byte address. ♦ The starting byte location can be anywhere within the selected SRAM page buffer, as shown in ♦ The page address must also be specified. ♦ If ...
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Chapter 4: Write and Program Commands Page to Buffer Compare (Program Verify) The Page to Buffer Compare command is not actually a programming command, but is primarily used to verify correct programming of nonvolatile data in an ISF memory page. ...
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R • Similarly, serially clock in a 24-bit Page Address. ♦ If using the default address scheme, see ♦ If using power-of-2 addressing, see • To end the command, drive CSB High on the falling edge of CLK. The CSB ...
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Chapter 4: Write and Program Commands EEPROM-Like, Byte-Level Write Operations The Spartan-3AN FPGA In-System Flash (ISF) memory includes small page size, SRAM page buffers, combined with flexible memory read and write commands. Consequently, the ISF memory can perform small, byte-level ...
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R Auto Page Rewrite This command is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion within a sector. This command combines two other operations, a Built-in Erase Auto Page ...
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Chapter 4: Write and Program Commands Table 4-9: Auto Page Rewrite Through Buffer Command Summary Pin Auto Page Rewrite (Buffer 1) MOSI Auto Page Rewrite (Buffer 2) Notes: 1. The Buffer 2 command is not available in the XC3S50AN because ...
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R Erase Commands The Spartan operations for maximum application flexibility. • The Page Erase • The Block Erase • The Sector Erase Sector Protect and Sector Lockdown Prevent Erase Operations The Sector Protection erase operations. A page, block, or sector ...
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Chapter 5: Erase Commands Page Erase The Page Erase command erases any individual page in the ISF memory array, as shown in Figure 5-2. Typically, the Page Erase command is used to prepare a page for a subsequent Buffer to ...
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... Page Address (4,096 pages Page Address (4,096 pages Table 5-4 and specified in the Spartan-3AN FPGA data bit (bit 7) of the Status Register Description Page Erase Time XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN www.xilinx.com Page Erase Table 5 Addressing Mode Power-of-2 Page Size (Bytes) Alignment ...
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Chapter 5: Erase Commands While the Page Erase operation is in progress, the FPGA can access any other portion of the ISF memory, including any of the following commands. • Read from or write to an SRAM page buffer, which ...
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... If using power-of-2 addressing, see • Drive CSB High on the falling edge of CLK to end the command. Table 5-6: Block Addressing Summary FPGA XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN Spartan-3AN FPGA In-System Flash User Guide UG333 (v2.1) January 15, 2009 High Address Middle Address Block Address ...
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... Block Address Block Address Block Address 0 0 Block Address Table 5-8 and specified in the READY/BUSY bit (bit 7) of the Description Block Erase Time XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide Low Address Don’t Care bits Don’ ...
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R Sector Erase The Sector Erase command erases any unprotected, unlocked sector in the main memory, as shown in Sector Erase MOSI MISO CSB CLK To perform a Sector Erase command, the FPGA application must perform the following actions. • ...
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Chapter 5: Erase Commands ♦ The page address and byte address bits, which follow the Sector Address, specify any valid address location within the sector which erased. ♦ If using the default address scheme, see ♦ If ...
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... R Table 5-10: Sector Addressing, Default Addressing Mode FPGA / Sector 23 22 XC3S50AN 0 0 Sector Sector 0a Sector 0b Sectors 1– 3 XC3S200AN Sector 0 0 XC3S400AN Sector 0a Sector 0b Sectors 1– 7 XC3S700AN Sector 0 0 Sector 0a Sector 0b Sectors 1– 15 XC3S1400AN Sector 0 0 Sector 0a Sector 0b Sectors 1– 15 Spartan-3AN FPGA In-System Flash User Guide UG333 (v2 ...
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... Chapter 5: Erase Commands Table 5-11: XC3S50AN, XC3S200AN, XC3S400AN Sector Boundaries Spartan-3AN FPGA XC3S50AN Pages per Sector 128 Addressing Default 264 Sector / Size Page 0a 0 0x00_0000 0x00_1000 1 128 0x01_0000 2 256 0x02_0000 3 384 0x03_0000 4 — — 5 — — 6 — — 7 — — Table 5-12: XC3S700AN, XC3S1400AN Sector Boundaries ...
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... Spartan-3AN FPGA In-System Flash User Guide UG333 (v2.1) January 15, 2009 Table 5-13 and specified in the READY/BUSY bit (bit 7) of the Description FPGA Sector Erase Time XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN www.xilinx.com Sector Erase Spartan-3AN FPGA data Status Register indicates Typ Max Units ...
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Chapter 5: Erase Commands 62 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
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... JEDEC-compatible device information ISF Memory Size 0011 = 1 Mbit: XC3S50AN 0111 = 4 Mbit: XC3S200AN or XC3S400AN 1001 = 8 Mbit: XC3S700AN 1011 = 16 Mbit: XC3S1400AN Table 6-1, the Status Register describes… Page to Buffer Compare (Program Verify) Sector Protection is presently enabled or not www ...
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Chapter 6: Status and Information Commands READY/BUSY READY/BUSY status of the In-System Flash (ISF) memory is indicated by bit 7 in the Status Register, as defined in Table 6-2: READY/BUSY READY/BUSY 0 1 There are several commands that cause a ...
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... Sectors defined in the Sector Lockdown Register Read www.xilinx.com Status Register Description command matches the data stored in Page to Buffer Bits and 2) Associated FPGA(s) 1 Mbit XC3S50AN XC3S200AN 4 Mbit XC3S400AN 8 Mbit XC3S700AN 16 Mbit XC3S1400AN Bit 1) Description Sector Protection Register. command. Page 65 ...
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... Spartan-3AN FPGA In-System Flash User Guide Table 6-6. FPGA Page Size XC3S50AN XC3S200AN 264 XC3S400AN XC3S700AN XC3S1400AN 528 XC3S50AN XC3S200AN 256 XC3S400AN XC3S700AN XC3S1400AN 512 at any time, including during any Read Status Byte ... Byte n XX ... XX Most-recent ... Status Byte READY/BUSY bit of the Status Register UG333 (v2 ...
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R See also Figure 1-3, page 12 Information Read The ISF memory supports JEDEC standards to enable systems and software to electronically query and identify the device while system. The ISF Information Read command complies with the ...
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... ISF memory is 0x1F. This value is different than the JEDEC code for Xilinx, which is 0x49. The Spartan-3AN FPGA product identifier is available via JTAG. Table 6-10: First Byte: Manufacturer Identifier FPGA All 68 Table Spartan-3AN FPGA XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN Table JEDEC Assigned Code (0x1F ...
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... FPGA densities, as shown in Status Register density code, shown in Table 6-11: Second Byte: Device Identifier (Part FPGA XC3S50AN (1 Mbit) XC3S200AN (4 Mbit) XC3S400AN (4 Mbit) XC3S700AN (8 Mbit) XC3S1400AN (16 Mbit) Memory Type/Product Version Code The third byte includes the remainder of the device identifier, as shown in • ...
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Chapter 6: Status and Information Commands 70 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
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R Power Management The Spartan V power rail to the Spartan-3AN FPGA. Note that write commands are not allowed CCAUX until 20 ms after VCCAUX has reached at least 2.5V. In general the ISF adds no significant current to the ...
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Chapter 7: Power Management CSB Figure 7-1: ISF Memory Enters Standby Mode when CSB is High Longer than 35 μs Thermal Considerations The ISF memory has negligible effect on the thermal considerations for the FPGA. The junction temperature of the ...
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R Sector-Based Program/Erase Protection The Spartan protect stored data against accidental or intentional changes. • The Sector Protection individual ISF memory sectors. • The Sector Lockdown essentially converting the Flash memory into read-only ROM. Once a sector is locked down, ...
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Chapter 8: Sector-Based Program/Erase Protection Sector Protection Using Sector Protection, the FPGA application protects selected memory sectors against erroneous program and erase cycles. There are five commands associated with the Sector Protection feature, as summarized in Table 8-2: Sector Protection ...
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... On the falling edge of CLK, serially clock in the four-byte Sector Protection Register Erase command sequence shown in each byte first. Spartan-3AN FPGA In-System Flash User Guide UG333 (v2.1) January 15, 2009 Available Sectors XC3S200AN XC3S700AN XC3S400AN XC3S1400AN Control Byte ◆ ◆ ◆ ◆ ◆ ...
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... Sector Protection Register is not guaranteed. can be erased regardless if sector protection is enabled or is erased, reprogram the register using the Sector Table 8-6 Sector Protection Register Value (byte locations corresponds to sector) XC3S700AN, XC3S1400AN (16 bytes) XC3S200AN, XC3S400AN (8 bytes) XC3S50AN (4 bytes) Byte 4 Byte 5 Byte 6 Byte 7 Sector 0 ...
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... The first data byte corresponds to Sector 0, the second data byte to Sector 1, and so on. The XC3S50AN FPGA requires four bytes. The XC3S200AN and the XC3S400AN FPGAs each require 8 bytes. The XC3S700AN and the XC3S1400AN FPGAs require 16 bytes. If the proper number of data bytes is not clocked in before the CSB pin is deasserted, then the protection status of the sectors corresponding to the unwritten bytes is not guaranteed ...
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... The first data byte corresponds to Sector 0, the second data byte to Sector 1, and so on. The XC3S50AN FPGA provides four bytes. The XC3S200AN and the XC3S400AN FPGAs each provide 8 bytes. The XC3S700AN and XC3S1400AN FPGAs provide 16 bytes. If the FPGA application reads more than required number of bytes from the Sector Protection Register, any additional data provided on the MISO pin is undefined ...
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R Sector Protection Enable The Sector Protection Enable command applies the protection level specified in the Protection application must perform the following actions using the SPI_ACCESS design primitive. • Drive CSB Low while CLK is High or on the rising ...
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Chapter 8: Sector-Based Program/Erase Protection There are two commands associated with the Sector Lockdown feature, as shown in Table 8-10. Table 8-10: Sector Lockdown Commands Command Sector Lockdown Register Read Sector Lockdown Program Sector Lockdown Program To lock down a ...
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... Spartan-3AN FPGA data READY/BUSY bit (bit 7) of the Status Register power supply is interrupted before the programming operation CCAUX Sector Lockdown Register Table 8-13. Available Sectors XC3S200AN XC3S700AN XC3S400AN XC3S1400AN Status Byte ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ...
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... The first data byte corresponds to Sector 0, the second data byte to Sector 1, and so on. The XC3S50AN FPGA provides four bytes. The XC3S200AN and the XC3S400AN FPGAs each provide 8 bytes. The XC3S700AN and the XC3S1400AN FPGAs provide 16 bytes. If the FPGA application reads more than required number of bytes from the Sector Lockdown Register, any additional data provided on the MISO pin is undefined ...
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R Security Register The Spartan Security Register, shown in Security Register The 128 bytes are further divided into two subfields. • The User-Defined Field (byte locations 0 through 63), can be programmed with any value at any time, but it ...
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Chapter 9: Security Register To issue the Security Register Program command sequence, the FPGA application must perform the following actions using the SPI_ACCESS design primitive. • Drive CSB Low while CLK is High or on the rising edge of CLK. ...
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R Security Register Read To read the using the SPI_ACCESS design primitive. • Drive CSB Low while CLK is High or on the rising edge of CLK. • On the falling edge of CLK, serially clock in the four-byte Security ...
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Chapter 9: Security Register 86 www.xilinx.com Spartan-3AN FPGA In-System Flash User Guide R UG333 (v2.1) January 15, 2009 ...
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... Table A-1 illustrates how the addressing mode affects total memory size. Table A-1: Default Addressing Mode vs. Power-of-2 Addressing Mode FPGA XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN How to Determine the Current Addressing Mode The Page Size outlined in ...
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Appendix A: Optional Power-of-2 Addressing Mode Permanently Changing to the Power-of-2 Addressing Mode To permanently change over from the 2 addressing mode, the programmer or FPGA application must perform the following steps. • Drive CSB Low while CLK is High, ...
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R Power-of-2 Addressing Table A-3 summarizes the address mapping for the optional power-of-2 addressing mode. Table A-3: Power-of-2 Addressing Mode FPGA Binary Address 3S50AN 3S200AN 3S400AN 3S700AN 3S1400AN Binary Address Power-of-2 Page Addressing Table A-4 summarizes how page addresses are ...
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... Table A-6: Sector Addressing, Power-of-2 Addressing Mode FPGA / Sector 23 22 Binary Address 0 0 XC3S50AN Sector 0 0 Sector 0a Sector 0b Sectors 1– 3 XC3S200AN Sector 0 0 XC3S400AN Sector 0a Sector 0b Sectors 1– 7 XC3S700AN Sector 0 0 Sector 0a Sector 0b Sectors 1– 15 XC3S1400AN Sector 0 0 Sector 0a Sector 0b Sectors 1– 15 ...