XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 56

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5: Erase Commands
56
Table 5-7: Block Addressing, Default Addressing Mode
A Low-to-High transition on the CSB input completes the command and the Flash then
erases the selected block of 8 pages. The erase operation is internally self-timed and
completes in the time shown in
sheet. During this time, the
whether the Block Erase operation is in progress or whether it has completed.
Table 5-8: Block Erase Time
While the Block Erase operation is in progress, the FPGA can access any other portion of
the ISF memory, including any of the following commands.
•
•
•
3S1400AN
3S200AN
3S400AN
3S700AN
3S50AN
Symbol
FPGA
Read from or write to an SRAM page buffer, which are not used during an erase
operation.
♦
♦
Status Register Read
Information Read
T
BE
Buffer Read
Buffer Write
23 22 21 20 19 18 17 16 15 14 13 12 11 10
0 0 0 0 0 0
0 0 0 0
0 0 0
0 0
Block Erase Time
High Address
Description
Block Address
www.xilinx.com
READY/BUSY
Block Address
Block Address
Table 5-8
Block Address
and specified in the
Middle Address
bit (bit 7) of the
Spartan-3AN FPGA In-System Flash User Guide
XC3S1400AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S50AN
X X X X X X X X X X X X X
FPGA
X X X X X X X X X X X X
X X X X X X X X X X X X
X X X X X X X X X X X X
9
Status Register
UG333 (v2.1) January 15, 2009
Don’t Care bits
Spartan-3AN FPGA data
8
Don’t Care bits
Don’t Care bits
Don’t Care bits
Typ
7
15
30
45
6
Low Address
5
Max
100
35
75
4
indicates
3
2
Units
ms
ms
ms
1
0
R