XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 31

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Random Read
Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
MOSI
MISO
CSB
CLK
CSB remains Low throughout entire transfer
0
0 0 0 0 1 0 1 1
Command Code (0x0B)
1
R
2
Figure 3-2: Fast Read Command Waveform (XC3S700AN, Default Address Mode)
3
4
5
6
7
•
•
•
•
The CSB signal must remain Low throughout the entire data transfer
command code, the 24 address bits, the 8 “don’t care” bits, and when reading the dummy
bytes and data bytes.
Upon reaching the end of a memory page, the ISF memory continues reading at the
beginning of the next page, as shown in
a page boundary. After reading the last bit in the memory array, the ISF continues reading
but returns to the beginning of the first page of memory. Again, there is no added delay
when wrapping around from the end of the array to the beginning of the array. A Low-to-
High transition on CSB terminates the read operation and the MISO output pin returns
High.
The Fast Read command bypasses both SRAM page buffers; the contents of the buffers
remain unchanged.
The Random Read command is best for smaller, random read operations. It has less initial
latency than the Fast Read command, but only operates up to 33 MHz, less than the
maximum frequency possible with the Fast Read command.
The Random Read command sequentially reads a continuous stream of data directly from
Flash memory bypassing the SRAM page buffers, as shown in
specifies an initial starting byte address in the ISF memory. The ISF memory incorporates
an internal address pointer that automatically increments on every clock cycle, allowing
one continuous read operation without requiring additional address sequences.
8
0 0 0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Address High Byte
Similarly, serially clock in a 24-bit page and byte starting address.
♦
♦
♦
Provide eight additional CLK cycles. At this point, the data supplied on the MOSI
input does not matter.
On the next falling CLK edge, the requested data serially appears on the MISO output
port.
♦
♦
To end the data transfer, deassert CSB High on the falling edge of CLK.
The starting byte location can be anywhere in the ISF memory array, located on
any page, as shown in
If using default addressing, see
If using power-of-2 addressing, see
Data is clocked out serially, most-significant bit first.
While CSB is Low, new data appears on the MISO output on every subsequent
falling CLK edge. The ISF memory automatically increments the implied address
counter through contiguous memory locations, as highlighted in
regardless of the address mode.
Address Middle Byte
www.xilinx.com
Figure
Address Low Byte
3-1.
Figure
Table 2-2, page 19
Table A-3, page 89
3-1. There is no added delay when crossing
X
X
Don’t Care Byte
X
X
X
.
X
X
.
X
Figure
MSB
40 41 42 43 44 45 46 47
First Data Byte
—
3-1. The command
Don’t Care
when writing the
Figure
Random Read
UG333_c3_01_020807
LSB MSB
48 49
3-1,
31