XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 40

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Write and Program Commands
Table 4-1: Summary of Write and Program Commands (Continued)
Buffer Write
40
Notes:
1. The Buffer 2 commands are not available in the XC3S50AN because it has only one SRAM page buffer.
Auto Page
Rewrite
Command
Refresh page
contents after 10,000
random program
operations to a sector
Best Application
The FPGA application can write data directly to one of the SRAM page buffers. Along with
the Buffer Read command, the FPGA application can randomly read or write the buffer
data without affecting the ISF memory array. Data is not written into nonvolatile Flash
memory using this command. Once the data within the buffer is finalized, the FPGA
application can subsequently copy contents of the buffer into the ISF memory array using
one of the following commands.
•
•
To issue a Buffer Write command, the FPGA application must perform the following
actions.
•
•
Buffer to Page Program with Built-in Erase
Buffer to Page Program without Built-in Erase
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the appropriate Buffer Write command
code, shown in
Buffer 1 Write
MOSI
MISO
Buffer 2 Write
CSB
CLK
Buffer 2
Command
Buffer 1
(0x58)
(0x59)
Code
Hex
SPI_ACCESS
(1)
Table
Frequency
Maximum
available on
Buffer 2 not
XC3S50AN
(0x84)
(0x87)
CLK
50
4-2, most-significant bit first.
www.xilinx.com
Figure 4-1: Buffer Write Command
Erase
Page
Yes
Write To
Buffer,
page
then
Spartan-3AN FPGA In-System Flash User Guide
Starting byte address
Automatically increments through
buffer, remains within buffer
Write Size
Minimum
N/A
Flash Memory Array
Write Size
Maximum
N/A
UG333 (v2.1) January 15, 2009
SRAM Page
UG333_c4_01_022307
Buffers
Affects
Yes
Simulation
Support
No
R