XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 44

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Write and Program Commands
Page Program Through Buffer
Table 4-6: Page Program Through Buffer Command Summary
44
Notes:
1. The Buffer 2 command is not available in the XC3S50AN because it has only one SRAM page buffer.
2. The Page Program Through Buffer command is supported in simulation.
MOSI
Pin
Through Buffer 2
Through Buffer 1
Page Program
Page Program
Command
Byte 1
0x82
0x85
•
Table 4-5: Page Programming Time, T
During the command execution time, the
indicates whether the Page Programming or Page Erase and Programming operation is in
progress or whether it has completed.
This operation combines the
Built-in Erase (Figure
address, including both the Page Address and the starting Byte Address within the SRAM
page buffer.
To issue a Page Program Through Buffer command, the FPGA application must perform
the following actions.
•
•
(1)
Symbol
If using the command without page erase…
♦
♦
♦
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the appropriate Page Program Through
Buffer command code, shown in
T
Default Addressing: See
Power-of-2 Addressing: See
PP
High Address Middle Address
The ISF memory programs the page with the data stored in the designated SRAM
page buffer.
This version of the command does not erase the selected page.
The operation is internally self-timed and completes in the Page Programming
time, T
Byte 2
24-bit Page and Starting Byte Address
Page Programming Time
PP
, shown in
Description
4-2) operations. The FPGA application must specify a full 24-bit
Byte 3
www.xilinx.com
Table 4-5
Buffer Write (Figure
Table 2-2, page 19
Table A-3, page 89
Table
and specified in the
Low Address
PP
READY/BUSY
Byte 4
4-2, most-significant bit first.
Spartan-3AN FPGA In-System Flash User Guide
XC3S1400AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S50AN
FPGA
4-1) and
Data +0
Byte 5
bit (bit 7) of the
Spartan-3AN FPGA data
Buffer to Page Program with
UG333 (v2.1) January 15, 2009
Page Buffer Data
Typ
Data +1
2
3
Byte 6
Max
Status Register
4
6
...
...
Byte n+4
Data +n
Units
sheet.
ms
ms
R