XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 13

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1-4: SPI_ACCESS Simulation Supported Commands
Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
Command
Fast Read
Random Read
Status Register Read
Information Read
Security Register
Read
Security Register
Program
Buffer Write
Simulation Support
R
Common Application
Reading a large block of contiguous data, if CLK frequency is above 33 MHz
Reading bytes from randomly-addressed locations, all read operations at 33
MHz or less
Check ready/busy for programming commands, result of compare, protection,
addressing mode, etc.
Read JEDEC Manufacturer and Device ID
Performs a read on the contents of the security register.
Programs the User-Defined Field in the Security Register
Write data to SRAM page buffer; when complete, transfer to ISF memory using
Buffer to Page Program command
1.
2.
3.
4.
5.
6.
7.
The SPI_ACCESS simulation model supports only a subset of the total commands that can
be run in hardware. The commands that are supported in the model are shown below in
Table
other commands are not supported in the simulation model, though they will work as
expected in hardware. For more information on the SPI_ACCESS primitive and simulation
model, please refer to the ISE® software, version 10.1 Synthesis and Simulation Design
Guide at:
or the Spartan-3A Libraries Guide at:
The FPGA application starts the command by driving the SPI_ACCESS CSB input
Low, while the CLK input is High. Subsequently, the CSB input must remain Low
throughout the entire transfer.
The
mentioned in
Consequently, the FPGA application clocks in the binary pattern “11010111” on the
MOSI input, synchronized to the falling edge of CLK.
The ISF memory captures the command sequence on the rising edge of CLK, as
indicated.
Before data appears, the MISO output is High.
After all eight command bits are transferred, the ISF memory provides the current
Status Register
most-significant bit first, synchronized to the falling edge of CLK.
The FPGA application captures the ISF status information on the rising edge of CLK.
After receiving the last bit of status information, the FPGA application drives the CSB
input High to end the transaction.
1-4. These have been tested and verified to work in the model and on silicon. All
http://toolbox.xilinx.com/docsan/xilinx10/books/docs/sim/sim.pdf
http://toolbox.xilinx.com/docsan/xilinx10/books/docs/spartan3a_hdl/spartan
3a_hdl.pdf
Status Register Read
“SPI Transactions,”
contents on the SPI_ACCESS MISO output. Again, the data appears
www.xilinx.com
command code is 0xD7, as detailed in
Accessing In-System Flash Memory After Configuration
all data is transferred most-significant bit first.
Table 6-7, page
Hex Command
Code
0x0B
0x03
0xD7
0x9F
0x77
0x9B
Buffer1- 0x84
Buffer2- 0x87
66. As
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