XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 66

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6: Status and Information Commands
Status Register Read
66
Page Size
Bit 0 in the
mode to access data within the ISF memory array, as defined in
Table 6-6: PAGE SIZE
The FPGA application can read the
internally self-timed program or erase operation. To read the Status Register, the FPGA
application must perform the following operations using the SPI_ACCESS design
primitive.
•
•
Table 6-7: Status Register Read (0xD7) Command
•
•
Notes:
1. The Status Register Read command is supported in simulation.
MOSI
MISO
Pin
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in Status Register Read command code,
0xD7, most-significant bit first.
On the clock cycle following the last bit of the command code, the ISF memory
presents the Status Register byte value on the SPI_ACCESS MISO pin.
♦
♦
To end the data transfer, drive CSB High on the falling edge of CLK. The CSB control
can be deasserted at any time as the command does not require the FPGA application
to read the entire
PAGE SIZE
Clock out the eight status bits, most-significant bit first.
While CSB is Low, the continuously updated Status Register value is repeated
every eight CLK clock cycles. For example, this capability allows the FPGA
application to continuously monitor the
until it returns to ‘1’.
0
1
Status Register
Command
Byte 1
0xD7
High
Status Register
Optional Power-of-2
Default Addressing
(Status Register
Addressing Mode
Addressing Mode
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indicates the size of each ISF memory page and the addressing
Mode
Status Register
value.
Bit 0)
Status Byte
Spartan-3AN FPGA In-System Flash User Guide
Byte 2
XX
READY/BUSY
XC3S1400AN
XC3S1400AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S50AN
XC3S50AN
at any time, including during any
FPGA
Read Status Byte
UG333 (v2.1) January 15, 2009
...
...
...
Table
bit of the
6-6.
Most-recent
Status Byte
Page Size
Status Register
Byte n
XX
264
528
256
512
R