XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 10

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1: Overview and SPI_ACCESS Interface
Table 1-3: SPI_ACCESS Primitive Attributes (Continued)
10
Attribute
SIM_MEM_FILE
SIM_FACTORY_ID
SIM_DELAY_TYPE
HDL Instantiation Examples
VHDL
Type
String
64-byte
Hex Value
String
The SPI_ACCESS design primitive must be instantiated in an HDL design; it cannot be
inferred by the logic synthesis software.
The SPI_ACCESS primitive requires that the
the SPI_ACCESS component and connect it to the other signals in the design.
Xilinx Unisim Library
The Xilinx Unisim library includes definitions for all the Spartan-3AN FPGA design
primitives, including the SPI_ACCESS primitive. Declare the Unisim library before the
entity declaration.
Instantiate SPI_ACCESS Primitive
Instantiate the SPI_ACCESS design primitive after the architecture declaration.
Connect each of the four SPI_ACCESS ports to a signal name in the FPGA application.
Caution!
the SPI_ACCESS primitive. Please see the
commands.
library
use
entity XXXX is
architecture Behavioral of XXXX is
begin
...
SPI_ACCESS_inst: SPI_ACCESS
generic map
)
port map
SIM_DEVICE =>
MISO => MISO_signal,
MOSI => MOSI_signal,
UNISIM.VComponents.all;
Allowed Values
Specified file and
“ACCURATE”,
directory name
Any 64-byte Hex
Value
“SCALED”
UNISIM;
Only a subset of the commands available in hardware are supported in simulation for
(
(
”3S700AN”
www.xilinx.com
Default
“NONE”
All locations
default to 0x00
“SCALED”
-- 1-bit SPI output data
-- 1-bit SPI input data
Simulation Support
Spartan-3AN FPGA In-System Flash User Guide
Xilinx Unisim Library
Description
Optionally specifies a hex file containing the
initialization memory content for the SPI
Memory.
Specifies the unique identifier value in the
Security Register
(the actual hardware value will be specific to
the particular device used). See
Register” in Chapter
Scales down some timing delays for faster
simulation run. “ACCURATE” = timing and
delays consistent with datasheet specs.
“SCALED” = timing numbers scaled back to
run faster simulation, behavior not affected.
UG333 (v2.1) January 15, 2009
section for a list of these
for simulation purposes
be declared. Instantiate
9.
“Security
R