XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 17

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Addressing Overview
Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
Addressing Modes
R
Sector 0 is further subdivided into two, individually protected sub-sectors, as shown in
Figure
always 8 pages while Sector 0b represents the remaining pages in Sector 0. Consequently,
the commands that operate on Sector 0 require slightly different addressing and control
than the same commands used on other sectors.
Spartan-3AN FPGA applications generally never make use of the split Sector 0 structure,
but applications must be aware that it exists in order to erase or protect Sector 0.
All commands that require an address use a 24-bit address field to select a sector, a block,
a page, or a byte location within a page. However, the In-System Flash memory supports
two different possible addressing schemes.
•
•
The
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expanded diagram of a page within the Flash array. The diagram also describes how the 24
bits in a command address field select a sector, block, page, or byte within a memory page.
Figure 2-5
Using the
power-of-2 page size found in other memories. For example, all Spartan-3AN FPGAs
except the XC3S1400AN use a 264-byte page, while the XC3S1400AN memory pages are
double the size at 528 bytes. The “extra” bits are useful for a variety of applications.
•
•
•
All Spartan-3AN FPGAs, as delivered, use the
Table
With an additional, special programming step, described in
Power-of-2 Addressing
addressing mode, which may be more natural for some applications.
More total nonvolatile memory for FPGA configuration or data storage applications.
Page pointers, linked address pointers, attributes, and status indicators for a Flash-
based file system.
Error detection/correction bits for extreme applications.
Default Addressing Mode
2-3. While the combined Sector 0 is the same size as all other sectors, Sector 0a is
shows the Flash memory array for the XC3S700AN FPGA, plus a detailed,
Figure 2-3: Sector 0 is Sub-divided into Two Smaller Sub-sectors
2-2. All Xilinx® software primarily supports this mode.
Default Addressing
is a similar diagram specific to the XC3S1400AN, which uses a larger page size.
3S50AN: (120 pages)
Others: (248 pages)
Sector 0a
Sector 0b
(8 pages )
www.xilinx.com
Mode”, Spartan-3AN FPGAs support a slightly different
Mode, each memory page is slightly larger than the typical
provides roughly 3% more total memory bits.
3S50AN: (128 pages)
Others: (256 pages)
All Other Sectors
Default Addressing
UG333_c2_03_022607
Appendix A, “Optional
Addressing Overview
Mode, detailed in
Figure 2-4,
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