XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 43

no-image

XC3S400AN-4FTG256I

Manufacturer Part Number
XC3S400AN-4FTG256I
Description
IC FPGA SPARTAN-3AN 256FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

Number Of Logic Elements/cells
8064
Number Of Labs/clbs
896
Total Ram Bits
368640
Number Of I /o
195
Number Of Gates
400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S400AN-4FTG256I
Manufacturer:
INFINEON
Quantity:
167
Part Number:
XC3S400AN-4FTG256I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S400AN-4FTG256I
Manufacturer:
FAIRCHIL..
Quantity:
698
Part Number:
XC3S400AN-4FTG256I
Manufacturer:
XILINX
0
Part Number:
XC3S400AN-4FTG256I
0
Table 4-3: Buffer to Page Program Command Summary
Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
Notes:
1. The Buffer 2 commands are not available in the XC3S50AN because it has only one SRAM page buffer.
2. The Buffer to Page Program command is supported in simulation.
MOSI
Pin
Buffer 2 to Page Program without Erase
Buffer 1 to Page Program without Erase
Buffer 2 to Page Program with Erase
R
Buffer 1 to Page Program with Erase
The CSB signal must remain Low throughout the entire data transfer.
A Low-to-High transition on the CSB input completes the command.
Table 4-4: Page Erase and Programming Time, T
Command
Symbol
Byte 1
0x83
0x86
0x88
0x89
T
Similarly, serially clock in a 24-bit page address.
To end the data transfer, drive CSB High on the falling edge of CLK.
If using the command with page erase…
PEP
If using the default address scheme, see
If using power-of-2 addressing, see
the ISF memory first erases the selected memory page
then programs the page with the data stored in the designated SRAM page buffer.
The operation is internally self-timed and completes in the Page Erase and
Programming time, T
FPGA data
Page Erase and Programming Time
sheet.
(1)
(1)
Description
www.xilinx.com
Default Addressing:
See
Power-of-2 Addressing:
See
PEP
High Address
Table 5-3, page 53
Table A-4, page 89
, shown in
Byte 2
Page Address in Buffer
Buffer to Page Program without Built-in Erase
Table 4-4
Table A-4, page
24-bit Page Address
Table 2-2, page 19
Middle Address
XC3S1400AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S50AN
PEP
and specified in the
FPGA
Byte 3
89.
or
Typ
14
17
Byte Address Unused
Table 5-3, page
Low Address
Don’t Care
Spartan-3AN
Max
Byte 4
35
40
XX
Units
53.
ms
ms
43

Related parts for XC3S400AN-4FTG256I