XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 42

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Write and Program Commands
42
•
To issue a Buffer to Page Program command, with or without built-in erase, the FPGA
application must perform the following actions.
•
•
The Buffer to Page Program without Built-in Erase command, shown in
simply programs an erased page with the data stored in the designated SRAM page
buffer.
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the appropriate command code, shown in
Table
Buffer 1 to Page Program with Erase
MOSI
MISO
Buffer 2 to Page Program with Erase
CSB
CLK
Buffer 1 to Page Program without Erase
MOSI
MISO
Buffer 2 to Page Program without Erase
4-3, most-significant bit first.
CSB
CLK
This command will not erase or
program a page within a sector
that is protected by Sector
Protect or Sector Lockdown
This command will not program
a page within a sector that is
protected by Sector Protect or
Sector Lockdown
Figure 4-3: Buffer to Page Program without Built-in Erase
Figure 4-2: Buffer to Page Program with Built-in Erase
SPI_ACCESS
Buffer 2 not available on XC3S50AN
SPI_ACCESS
www.xilinx.com
Spartan-3AN FPGA In-System Flash User Guide
Selected ISF page is first erased,
then programmed with Buffer data .
(0x83)
(0x86)
READY/BUSY
Buffer data is written to an erased
page.
Status Register
READY/BUSY
7
0 = Page Erase and Program in progress
1 = Selected page now erased/programmed
Flash Memory Array
Status Register
6
(0x88)
(0x89)
7
0 = Page programming in progress
1 = Page programming complete
T
PEP
Flash Memory Array
5
6
Page address
T
UG333_c4_02_082307
4
= 35 to 40 ms
PP
UG333 (v2.1) January 15, 2009
5
3
= 4 to 6 ms
Page address
4
2
3
1
UG333_c4_03_082307
2
0
1
Figure
0
4-3,
R