XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 41

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4-2: Buffer Write Command Summary
Buffer to Page Program with Built-in Erase
Buffer to Page Program without Built-in Erase
Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
Notes:
1. The Buffer 2 Write command is not available in the XC3S50AN because it has only one SRAM page buffer.
2. The Buffer Write command is supported in simulation.
MOSI
Pin
Buffer 2 Write
Buffer 1 Write
Command
R
Byte 1
0x84
0x87
(1)
•
•
•
The CSB signal must remain Low throughout the entire data transfer.
The ISF memory offers two similar commands that copy the contents of an SRAM page
buffer to a selected memory page. One version erases the selected memory page before
programming the page, while the second version programs a previously-erased page with
data from an SRAM page buffer.
•
High Address
Similarly, serially clock in a 24-bit starting byte address. Any page address
information is ignored.
♦
♦
♦
On the next falling CLK edge, serially supply the write data on the MOSI port.
♦
♦
♦
To end the data transfer, drive CSB High on the falling edge of CLK.
The Buffer to Page Program with Built-in Erase command, shown in
erases the selected memory page and then programs the page with the data stored in
the designated SRAM page buffer.
Unused
Byte 2
0x00
The starting byte location can be anywhere within the selected SRAM page buffer,
as shown in
If using the default address scheme, see
If using power-of-2 addressing, see
Data is clocked in serially, most-significant bit first.
While CSB is Low, present new data on the MOSI pin on every subsequent falling
CLK edge. The ISF memory automatically increments the implied address
counter through the SRAM page buffer, as highlighted in
-
-
If the transaction reaches the end of a buffer, the ISF memory continues writing
back at the beginning of the buffer.
The first data byte written is stored in Byte Address + 0
The second data byte written is stored in Byte Address + 1, and so on.
24-bit Starting Byte Address
Default Addressing:
See
Power-of-2 Addressing:
See
Middle Address
Figure
Table 2-2, page 19
Table A-3, page 89
Byte 3
Byte Address in Buffer
www.xilinx.com
4-1.
Low Address
Byte 4
Table A-3, page 89
Buffer to Page Program with Built-in Erase
Table 2-2, page 19
Data +0
Byte 5
.
Page Buffer Data
.
Figure
Data +1
Byte 6
4-1.
Figure
...
Byte n+4
Data +n
4-2, first
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