XC3S400AN-4FTG256I Xilinx Inc, XC3S400AN-4FTG256I Datasheet - Page 26

• Manufacturer Part Number: XC3S400AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FTG256I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 195
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2: In-System Flash Memory Architecture
MultiBoot Configuration Bitstream Guidelines
26
Align to Flash Sector Boundaries
Additional Memory Space Required for DCM_WAIT
The following guidelines are recommended when storing multiple configuration files in
the In-System Flash (ISF) memory.
Spartan-3AN FPGA MultiBoot addressing is flexible enough to allow a bitstream to begin
at any byte boundary. However, ideally, a Spartan-3AN FPGA MultiBoot configuration
image should be aligned to a sector boundary. This way, one FPGA bitstream can be
updated without affecting others in the Flash. Aligning to an ISF sector boundary provides
the additional advantage of allowing independent protection or lockdown of the
bitstreams.
Multiple configuration images should be spaced more than 5 ms apart so that the second
configuration file does not interfere with a delayed start-up following programming with
the first configuration file. Start-up can be delayed by waiting for lock from one or more
Digital Clock Managers (DCMs), a slow or missing STARTUP user clock, or holding the
DONE pin Low.
Each DCM provides an option setting that, during configuration, causes the FPGA to wait
for the DCM to acquire and lock to its input clock frequency before the DCM allows the
FPGA to finish the configuration process. The lock time, which is specified in the
3AN FPGA data
Even if the FPGA is waiting for one or more DCMs to lock before completing
configuration, the FPGA’s configuration controller continues searching for the next
synchronization word. If two adjacent MultiBoot images are placed one immediately
following the other, and the first FPGA bitstream contains a DCM with the DCM_WAIT
option set, then potential configuration problems can occur. If the controller sees the
synchronization word in the second FPGA bitstream before completing the current
configuration, it starts interpreting data from the second bitstream. However, the FPGA’s
configuration logic may complete the current configuration even though the FPGA has
read data from the second bitstream.
Spacing MultiBoot bitstreams sufficiently apart in memory prevents the FPGA from ever
seeing the second synchronization word. For more details, see
Generation Configuration User
Caution!
spacing between MultiBoot configuration images!
FPGA applications that use the DCM_WAIT option on a DCM must ensure sufficient
sheet, depends on the DCM mode, and the input clock frequency.
www.xilinx.com
Guide, Chapter 14, Reconfiguration and MultiBoot.
Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
UG332: Spartan-3
Spartan-
R