MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 85

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
SEC
SEI
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
STHX opr
STOP
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
SWI
TAP
TAX
TPA
Source
Form
Subtract with Carry
Set Carry Bit
Set Interrupt Mask
Store A in M
Store H:X in M
Enable IRQ Pin; Stop Oscillator
Store X in M
Subtract
Software Interrupt
Transfer A to CCR
Transfer A to X
Transfer CCR to A
Operation
Table 6-1. Instruction Set Summary (Sheet 7 of 8)
Central Processor Unit (CPU)
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
I ← 0; Stop Oscillator
A ← (A) – (M) – (C)
(M:M + 1) ← (H:X)
SP ¨ (SP) – 1; I ¨ 1
A ← (A) – (M)
Description
CCR ← (A)
A ← (CCR)
M ← (A)
M ← (X)
X ← (A)
C ← 1
I ← 1
V H I N Z C
– – – – – 1 INH
– – 1 – – – INH
0 – –
0 – –
– – 0 – – – INH
0 – –
– – 1 – – – INH
– – – – – – INH
– – – – – – INH
Effect on CCR
– –
– –
Central Processor Unit (CPU)
Instruction Set Summary
–
– DIR
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
INH
Technical Data
9ED2
9ED7
9EEF
9EDF
9ED0
9EE2
9EE7
9EE0
C2
D2
C7
D7
BF
CF
DF
EF
C0
D0
A2
B2
E2
F2
99
9B
B7
E7
F7
35
8E
FF
A0
B0
E0
F0
83
84
97
85
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
dd
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
85
2
3
4
4
3
2
4
5
1
2
3
4
4
3
2
4
5
4
1
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
9
2
1
1