MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 337

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.6.4 SIM Break Flag Control Register
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
The SIM break flag control register (SBFCR) contains a bit that enables
software to clear status bits while the MCU is in a break state.
BCFE — Break Clear Flag Enable Bit
Reset:
dress:
Read:
Write:
Ad-
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
HIBYTE EQU
LOBYTE EQU
DOLO
RETURN PULH
1 = Status bits clearable during break
0 = Status bits not clearable during break
Figure 20-8. SIM Break Flag Control Register (SBFCR)
$FE03
BCFE
Bit 7
R
0
BRCLR BW,BSR, RETURN ; See if wait mode or stop
TST
BNE
DEC
DEC
RTI
= Reserved
5
6
LOBYTE,SP
DOLO
HIBYTE,SP
LOBYTE,SP
R
6
Break (BRK)
Figure 20-7. Example Code
R
5
R
4
; If not BW, do RTI
; mode was exited by break.
; If RETURNLO is not 0,
; then just decrement low byte.
; Else deal with high byte also.
; Point to WAIT/STOP opcode.
; Restore H register.
R
3
R
2
Break Module Registers
R
1
Technical Data
Break (BRK)
Bit 0
R
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