MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 47

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
U = Unaffected
nate
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Addr.
↓
IRQ Status/Control Reg-
ADC Data Register High
ADC Status and Control
ADC Data Register Low
TIMB Counter Register
TIMB Counter Register
TIMB Counter Modulo
TIMB Status/Control
ADC Clock Register
Register High (TB-
Register (ADSCR)
Register (TBSC)
Register Name
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 10)
See page 303.
See page 319.
See page 322.
See page 323.
See page 324.
See page 238.
See page 240.
See page 240.
See page 241.
X = Indetermi-
(TBCNTH)
(TBCNTL)
(ADCLK)
(ADRH)
MODH)
(ADRL)
(ISCR)
High
ister
Low
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read: Bit 15
Read;
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
COCO
ADIV2
Bit 15
Bit 7
AD7
TOF
Bit 7
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
1
= Reserved
ADIV1
Bit 14
Bit 14
AIEN
TOIE
Bit 6
AD6
Memory Map
R
R
R
R
R
6
0
0
0
0
0
0
0
0
1
TSTOP
ADCO
ADIV0
Bit 13
Bit 13
AD5
Bit 5
R
R
R
R
R
5
0
0
0
0
0
1
0
0
1
ADICLK
ADCH4
Unaffected by reset
Unaffected by reset
TRST
Bit 12
Bit 12
Bold
AD4
Bit 4
Unimplemented
Unimplemented
R
R
R
R
R
4
0
0
1
0
0
0
0
0
0
1
ered
= Buff-
MODE1
ADCH3
Bit 11
Bit 11
IRQF
Bit 3
AD3
R
R
R
R
R
3
0
1
0
0
0
0
0
0
1
MODE0
ADCH2 ADCH1 ADCH0
ACK1
Bit 10
Bit 10
Bit 2
AD2
PS2
R
R
R
R
2
0
0
1
0
1
0
0
0
1
= Unimplemented
IMASK1 MODE1
AD9
AD1
PS1
Bit 9
Bit 1
Bit 9
Technical Data
R
R
R
R
1
0
1
0
0
0
0
0
1
Memory Map
I/O Section
Bit 0
Bit 8
Bit 0
Bit 8
AD8
AD0
PS0
R
R
R
R
R
0
1
0
0
0
0
0
1
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