MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 234

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Timer Interface B (TIMB)
12.4.4.3 PWM Initialization
Technical Data
234
NOTE:
NOTE:
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.
To ensure correct operation when generating unbuffered or buffered
PWM signals, use this initialization procedure:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable
0 percent duty cycle generation and removes the ability of the channel
to self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
1. In the TIMB status and control register (TBSC):
2. In the TIMB counter modulo registers (TBMODH–TBMODL), write
3. In the TIMB channel x registers (TBCHxH–TBCHxL), write the
4. In TIMB channel x status and control register (TBSCx):
5. In the TIMB status control register (TBSC), clear the TIMB stop bit,
a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter and prescaler by setting the TIMB
the value for the required PWM period.
value for the required pulse width.
a. Write 0:1 (for unbuffered output compare or PWM signals) or
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
TSTOP.
reset bit, TRST.
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB–MSxA. See
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. See
Timer Interface B (TIMB)
Table
MC68HC908MR8 — Rev 4.1
12-2.
Freescale Semiconductor
Table
12-2.