MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 363

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

H — The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
high byte — The most significant eight bits of a word.
illegal address — An address not within the memory map.
illegal opcode — A non-existent opcode.
I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts
index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The
input/output (I/O) — Input/output interfaces between a computer system and the external world.
instructions — Operations that a CPU can perform. Instructions are expressed by programmers
interrupt — A temporary break in the sequential execution of a program to respond to signals
interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to
I/O — See input/output (I/0).
IRQ — See external interrupt module (IRQ).
jitter — Short-term signal instability.
latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
the low-order four bits of the accumulator value to the high-order four bits. The half-carry bit
is required for binary-coded decimal arithmetic operations. The decimal adjust accumulator
(DAA) instruction uses the state of the H and C bits to determine the appropriate correction
factor.
through F.
are disabled.
lower byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X
to determine the effective address of the operand. H:X can also serve as a temporary data
storage location.
A CPU reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
as assembly language mnemonics. A CPU interprets an opcode and its associated
operand(s) and instruction.
from peripheral devices by executing a subroutine.
execute a subroutine.
is applied to the circuit.
Technical Data
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