MCHC908MR8CFAE Freescale Semiconductor, MCHC908MR8CFAE Datasheet - Page 76

• Manufacturer Part Number: MCHC908MR8CFAE
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908MR8CFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Central Processor Unit (CPU)
6.4.5 Condition Code Register
Technical Data
76
The 8-bit condition code register (CCR) contains the interrupt mask and
five flags that indicate the results of the instruction just executed. Bit 6
and bit 5 are set permanently to logic 1. The functions of the condition
code register are described here.
V — Overflow Flag
H — Half-Carry Flag
I — Interrupt Mask
Write:
Read
Re-
set:
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA
instruction uses the states of the H and C flags to determine the
appropriate correction factor.
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
:
1 = Overflow
0 = No overflow
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
X = Indeterminate
Bit 7
V
X
Central Processor Unit (CPU)
Figure 6-6. Condition Code Register (CCR)
6
1
1
5
1
1
H
X
4
3
1
I
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
N
X
2
X
1
Z
Bit 0
C
X